
John C. Hong
Examiner (ID: 1779, Phone: (571)272-4529 , Office: P/3726 )
| Most Active Art Unit | 3726 |
| Art Unit(s) | 3726 |
| Total Applications | 2343 |
| Issued Applications | 1904 |
| Pending Applications | 53 |
| Abandoned Applications | 396 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10307513
[patent_doc_number] => 20150192514
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-07-09
[patent_title] => 'Scatterometry Metrology Methods And Methods Of Modeling Formation Of A Vertical Region Of A Multilayer Semiconductor Substrate To Comprise A Scatterometry Target'
[patent_app_type] => utility
[patent_app_number] => 14/147417
[patent_app_country] => US
[patent_app_date] => 2014-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4374
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14147417
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/147417 | Scatterometry metrology methods and methods of modeling formation of a vertical region of a multilayer semiconductor substrate to comprise a scatterometry target | Jan 2, 2014 | Issued |
Array
(
[id] => 11830943
[patent_doc_number] => 09727686
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-08-08
[patent_title] => 'Method for finding non-essential flip flops in a VLSI design that do not require retention in standby mode'
[patent_app_type] => utility
[patent_app_number] => 14/758927
[patent_app_country] => US
[patent_app_date] => 2014-01-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 21
[patent_no_of_words] => 11977
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14758927
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/758927 | Method for finding non-essential flip flops in a VLSI design that do not require retention in standby mode | Jan 1, 2014 | Issued |
Array
(
[id] => 10301580
[patent_doc_number] => 20150186580
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-07-02
[patent_title] => 'SYSTEM AND METHOD FOR AMPLIFIER DESIGN'
[patent_app_type] => utility
[patent_app_number] => 14/144695
[patent_app_country] => US
[patent_app_date] => 2013-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8027
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14144695
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/144695 | System and method for amplifier design | Dec 30, 2013 | Issued |
Array
(
[id] => 9437647
[patent_doc_number] => 20140115554
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-04-24
[patent_title] => 'METHOD OF GENERATING A LAYOUT OF AN INTEGRATED CIRCUIT COMPRISING BOTH STANDARD CELLS AND AT LEAST ONE MEMORY INSTANCE'
[patent_app_type] => utility
[patent_app_number] => 14/145157
[patent_app_country] => US
[patent_app_date] => 2013-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 9643
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14145157
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/145157 | METHOD OF GENERATING A LAYOUT OF AN INTEGRATED CIRCUIT COMPRISING BOTH STANDARD CELLS AND AT LEAST ONE MEMORY INSTANCE | Dec 30, 2013 | Abandoned |
Array
(
[id] => 10301584
[patent_doc_number] => 20150186583
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-07-02
[patent_title] => 'SYSTEM FOR AND METHOD OF TUNING CLOCK NETWORKS CONSTRUCTED USING VARIABLE DRIVE-STRENGTH CLOCK INVERTERS WITH VARIABLE DRIVE-STRENGTH CLOCK DRIVERS BUILT OUT OF A SMALLER SUBSET OF BASE CELLS'
[patent_app_type] => utility
[patent_app_number] => 14/141104
[patent_app_country] => US
[patent_app_date] => 2013-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 7639
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14141104
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/141104 | System for and method of tuning clock networks constructed using variable drive-strength clock inverters with variable drive-strength clock drivers built out of a smaller subset of base cells | Dec 25, 2013 | Issued |
Array
(
[id] => 10002489
[patent_doc_number] => 09046573
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-06-02
[patent_title] => 'Addressable test arrays for characterizing integrated circuit device parameters'
[patent_app_type] => utility
[patent_app_number] => 14/137772
[patent_app_country] => US
[patent_app_date] => 2013-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 15
[patent_no_of_words] => 7337
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14137772
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/137772 | Addressable test arrays for characterizing integrated circuit device parameters | Dec 19, 2013 | Issued |
Array
(
[id] => 9758989
[patent_doc_number] => 20140289689
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-09-25
[patent_title] => 'WIRING INSPECTION APPARATUS AND WIRING INSPECTION METHOD'
[patent_app_type] => utility
[patent_app_number] => 14/132542
[patent_app_country] => US
[patent_app_date] => 2013-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 9170
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14132542
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/132542 | Wiring inspection apparatus and wiring inspection method | Dec 17, 2013 | Issued |
Array
(
[id] => 10284820
[patent_doc_number] => 20150169818
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-06-18
[patent_title] => 'PATTERN-BASED VIA REDUNDANCY INSERTION'
[patent_app_type] => utility
[patent_app_number] => 14/132926
[patent_app_country] => US
[patent_app_date] => 2013-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3955
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14132926
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/132926 | Pattern-based via redundancy insertion | Dec 17, 2013 | Issued |
Array
(
[id] => 9847820
[patent_doc_number] => 08949754
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-02-03
[patent_title] => 'System, method, and computer program product for verification using X-propagation'
[patent_app_type] => utility
[patent_app_number] => 14/108902
[patent_app_country] => US
[patent_app_date] => 2013-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5405
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14108902
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/108902 | System, method, and computer program product for verification using X-propagation | Dec 16, 2013 | Issued |
Array
(
[id] => 9940921
[patent_doc_number] => 08990752
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-03-24
[patent_title] => 'Method for automatic design of an electronic circuit, corresponding system, and computer program product'
[patent_app_type] => utility
[patent_app_number] => 14/108462
[patent_app_country] => US
[patent_app_date] => 2013-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 16
[patent_no_of_words] => 7750
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14108462
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/108462 | Method for automatic design of an electronic circuit, corresponding system, and computer program product | Dec 16, 2013 | Issued |
Array
(
[id] => 9540370
[patent_doc_number] => 20140165017
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-06-12
[patent_title] => 'PHYSICS-BASED RELIABILITY MODEL FOR LARGE-SCALE CMOS CIRCUIT DESIGN'
[patent_app_type] => utility
[patent_app_number] => 14/100712
[patent_app_country] => US
[patent_app_date] => 2013-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 12766
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14100712
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/100712 | Physics-based reliability model for large-scale CMOS circuit design | Dec 8, 2013 | Issued |
Array
(
[id] => 10276323
[patent_doc_number] => 20150161320
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-06-11
[patent_title] => 'SCATTERING BAR OPTIMIZATION APPARATUS AND METHOD'
[patent_app_type] => utility
[patent_app_number] => 14/100673
[patent_app_country] => US
[patent_app_date] => 2013-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6750
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14100673
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/100673 | SCATTERING BAR OPTIMIZATION APPARATUS AND METHOD | Dec 8, 2013 | Abandoned |
Array
(
[id] => 10131264
[patent_doc_number] => 09165100
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-10-20
[patent_title] => 'Methods and apparatus to map schematic elements into a database'
[patent_app_type] => utility
[patent_app_number] => 14/097432
[patent_app_country] => US
[patent_app_date] => 2013-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5046
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14097432
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/097432 | Methods and apparatus to map schematic elements into a database | Dec 4, 2013 | Issued |
Array
(
[id] => 10847879
[patent_doc_number] => 08875080
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-10-28
[patent_title] => 'Programmable macros for metal/via programmable gate array integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 14/096292
[patent_app_country] => US
[patent_app_date] => 2013-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 31
[patent_no_of_words] => 3574
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 227
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14096292
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/096292 | Programmable macros for metal/via programmable gate array integrated circuits | Dec 3, 2013 | Issued |
Array
(
[id] => 9398690
[patent_doc_number] => 20140096096
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-04-03
[patent_title] => 'ANALOG CIRCUIT SIMULATOR AND ANALOG CIRCUIT VERIFICATION METHOD'
[patent_app_type] => utility
[patent_app_number] => 14/095142
[patent_app_country] => US
[patent_app_date] => 2013-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3972
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14095142
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/095142 | Analog circuit simulator and analog circuit verification method | Dec 2, 2013 | Issued |
Array
(
[id] => 10413558
[patent_doc_number] => 20150298569
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-10-22
[patent_title] => 'VEHICLE'
[patent_app_type] => utility
[patent_app_number] => 14/647329
[patent_app_country] => US
[patent_app_date] => 2013-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6369
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14647329
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/647329 | Vehicle | Nov 25, 2013 | Issued |
Array
(
[id] => 9847818
[patent_doc_number] => 08949752
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-02-03
[patent_title] => 'System and method of emulating multiple custom prototype boards'
[patent_app_type] => utility
[patent_app_number] => 14/089522
[patent_app_country] => US
[patent_app_date] => 2013-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4680
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14089522
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/089522 | System and method of emulating multiple custom prototype boards | Nov 24, 2013 | Issued |
Array
(
[id] => 10834849
[patent_doc_number] => 08863045
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-10-14
[patent_title] => 'Optical proximity correction method based on hybrid simulation model'
[patent_app_type] => utility
[patent_app_number] => 14/086222
[patent_app_country] => US
[patent_app_date] => 2013-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 1701
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14086222
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/086222 | Optical proximity correction method based on hybrid simulation model | Nov 20, 2013 | Issued |
Array
(
[id] => 10401753
[patent_doc_number] => 20150286762
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-10-08
[patent_title] => 'LOGIC CONFIGURATION METHOD FOR RECONFIGURABLE SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/443635
[patent_app_country] => US
[patent_app_date] => 2013-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 15426
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14443635
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/443635 | Logic configuration method for reconfigurable semiconductor device | Nov 18, 2013 | Issued |
Array
(
[id] => 9599312
[patent_doc_number] => 20140195993
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-07-10
[patent_title] => 'THREE-DIMENSIONAL MASK MODEL FOR PHOTOLITHOGRAPHY SIMULATION'
[patent_app_type] => utility
[patent_app_number] => 14/081386
[patent_app_country] => US
[patent_app_date] => 2013-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7151
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14081386
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/081386 | Three-dimensional mask model for photolithography simulation | Nov 14, 2013 | Issued |