Search

John C. Hong

Examiner (ID: 1779, Phone: (571)272-4529 , Office: P/3726 )

Most Active Art Unit
3726
Art Unit(s)
3726
Total Applications
2343
Issued Applications
1904
Pending Applications
53
Abandoned Applications
396

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9381386 [patent_doc_number] => 20140084867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-27 [patent_title] => 'SECONDARY BATTERY DEVICE AND BATTERY CAPACITY ESTIMATION SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/777093 [patent_app_country] => US [patent_app_date] => 2013-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6886 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13777093 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/777093
SECONDARY BATTERY DEVICE AND BATTERY CAPACITY ESTIMATION SYSTEM Feb 25, 2013 Abandoned
Array ( [id] => 9683118 [patent_doc_number] => 20140239881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'UNIVERSAL BATTERY CHARGER SYSTEM AND METHOD' [patent_app_type] => utility [patent_app_number] => 13/777075 [patent_app_country] => US [patent_app_date] => 2013-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1986 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13777075 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/777075
Universal battery charger system and method Feb 25, 2013 Issued
Array ( [id] => 9444366 [patent_doc_number] => 08713502 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-04-29 [patent_title] => 'Methods and systems to reduce a number of simulations in a timing analysis' [patent_app_type] => utility [patent_app_number] => 13/776892 [patent_app_country] => US [patent_app_date] => 2013-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12083 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13776892 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/776892
Methods and systems to reduce a number of simulations in a timing analysis Feb 25, 2013 Issued
Array ( [id] => 10645890 [patent_doc_number] => 09362772 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-07 [patent_title] => 'System and method for balancing voltages' [patent_app_type] => utility [patent_app_number] => 13/776913 [patent_app_country] => US [patent_app_date] => 2013-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3152 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13776913 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/776913
System and method for balancing voltages Feb 25, 2013 Issued
Array ( [id] => 9472563 [patent_doc_number] => 08726212 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-13 [patent_title] => 'Streamlined parasitic modeling with common device profile' [patent_app_type] => utility [patent_app_number] => 13/773452 [patent_app_country] => US [patent_app_date] => 2013-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3892 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13773452 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/773452
Streamlined parasitic modeling with common device profile Feb 20, 2013 Issued
Array ( [id] => 9630145 [patent_doc_number] => 08799838 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-05 [patent_title] => 'Equivalence checking method, equivalence checking program, and equivalence checking device' [patent_app_type] => utility [patent_app_number] => 13/769892 [patent_app_country] => US [patent_app_date] => 2013-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 91 [patent_figures_cnt] => 110 [patent_no_of_words] => 62987 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13769892 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/769892
Equivalence checking method, equivalence checking program, and equivalence checking device Feb 18, 2013 Issued
Array ( [id] => 9652379 [patent_doc_number] => 08806415 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-08-12 [patent_title] => 'Integrated circuit pad modeling' [patent_app_type] => utility [patent_app_number] => 13/768112 [patent_app_country] => US [patent_app_date] => 2013-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6735 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13768112 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/768112
Integrated circuit pad modeling Feb 14, 2013 Issued
Array ( [id] => 9658898 [patent_doc_number] => 20140229903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-14 [patent_title] => 'OPTICAL PROXIMITY CORRECTION FOR TOPOGRAPHICALLY NON-UNIFORM SUBSTRATES' [patent_app_type] => utility [patent_app_number] => 13/763292 [patent_app_country] => US [patent_app_date] => 2013-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5550 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13763292 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/763292
Optical proximity correction for topographically non-uniform substrates Feb 7, 2013 Issued
Array ( [id] => 9714580 [patent_doc_number] => 08839183 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-16 [patent_title] => 'Method and apparatus for derived layers visualization and debugging' [patent_app_type] => utility [patent_app_number] => 13/756022 [patent_app_country] => US [patent_app_date] => 2013-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 4929 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13756022 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/756022
Method and apparatus for derived layers visualization and debugging Jan 30, 2013 Issued
Array ( [id] => 9156912 [patent_doc_number] => 08589826 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-19 [patent_title] => 'Photomask constructions having liners of specified compositions along sidewalls of multi-layered structures' [patent_app_type] => utility [patent_app_number] => 13/750963 [patent_app_country] => US [patent_app_date] => 2013-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4986 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13750963 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/750963
Photomask constructions having liners of specified compositions along sidewalls of multi-layered structures Jan 24, 2013 Issued
Array ( [id] => 9611793 [patent_doc_number] => 08788982 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-22 [patent_title] => 'Layout design defect repair using inverse lithography' [patent_app_type] => utility [patent_app_number] => 13/740651 [patent_app_country] => US [patent_app_date] => 2013-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 8103 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13740651 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/740651
Layout design defect repair using inverse lithography Jan 13, 2013 Issued
Array ( [id] => 8831869 [patent_doc_number] => 20130132914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-23 [patent_title] => 'Method and Apparatus for Placing Transistors In Proximity to Through-Silicon Vias' [patent_app_type] => utility [patent_app_number] => 13/740439 [patent_app_country] => US [patent_app_date] => 2013-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11625 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13740439 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/740439
Placing transistors in proximity to through-silicon vias Jan 13, 2013 Issued
Array ( [id] => 9156915 [patent_doc_number] => 08589829 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-19 [patent_title] => 'Three-dimensional mask model for photolithography simulation' [patent_app_type] => utility [patent_app_number] => 13/736929 [patent_app_country] => US [patent_app_date] => 2013-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7215 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13736929 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/736929
Three-dimensional mask model for photolithography simulation Jan 7, 2013 Issued
Array ( [id] => 10041222 [patent_doc_number] => 09081929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-14 [patent_title] => 'Systems, processes and computer-accessible medium for providing logic encryption utilizing fault analysis' [patent_app_type] => utility [patent_app_number] => 13/735642 [patent_app_country] => US [patent_app_date] => 2013-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6084 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13735642 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/735642
Systems, processes and computer-accessible medium for providing logic encryption utilizing fault analysis Jan 6, 2013 Issued
Array ( [id] => 9559914 [patent_doc_number] => 20140177626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'DIE-STACKED DEVICE WITH PARTITIONED MULTI-HOP NETWORK' [patent_app_type] => utility [patent_app_number] => 13/726142 [patent_app_country] => US [patent_app_date] => 2012-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7815 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13726142 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/726142
Die-stacked device with partitioned multi-hop network Dec 22, 2012 Issued
Array ( [id] => 9564059 [patent_doc_number] => 20140181772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'DETERMINING HIGH QUALITY INITIAL CANDIDATE SINK LOCATIONS FOR ROBUST CLOCK NETWORK DESIGN' [patent_app_type] => utility [patent_app_number] => 13/724212 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6375 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13724212 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/724212
DETERMINING HIGH QUALITY INITIAL CANDIDATE SINK LOCATIONS FOR ROBUST CLOCK NETWORK DESIGN Dec 20, 2012 Abandoned
Array ( [id] => 9558328 [patent_doc_number] => 20140176041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'SEMICONDUCTOR THERMOELECTRIC MODULE CHARGER FOR MOBILE COMPUTING DEVICE' [patent_app_type] => utility [patent_app_number] => 13/722387 [patent_app_country] => US [patent_app_date] => 2012-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3733 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13722387 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/722387
SEMICONDUCTOR THERMOELECTRIC MODULE CHARGER FOR MOBILE COMPUTING DEVICE Dec 19, 2012 Abandoned
Array ( [id] => 10125811 [patent_doc_number] => 09160185 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-13 [patent_title] => 'Apparatus and method for active balancing of series cells and series packs in a battery system' [patent_app_type] => utility [patent_app_number] => 13/722673 [patent_app_country] => US [patent_app_date] => 2012-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2532 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13722673 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/722673
Apparatus and method for active balancing of series cells and series packs in a battery system Dec 19, 2012 Issued
Array ( [id] => 9558336 [patent_doc_number] => 20140176048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'AC ADAPTER FOR ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 13/722055 [patent_app_country] => US [patent_app_date] => 2012-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3918 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13722055 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/722055
AC adapter for electronic device Dec 19, 2012 Issued
Array ( [id] => 10112275 [patent_doc_number] => 09147694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-29 [patent_title] => 'Density gradient cell array' [patent_app_type] => utility [patent_app_number] => 13/721552 [patent_app_country] => US [patent_app_date] => 2012-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6210 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13721552 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/721552
Density gradient cell array Dec 19, 2012 Issued
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