Search

John C. Hong

Examiner (ID: 1779, Phone: (571)272-4529 , Office: P/3726 )

Most Active Art Unit
3726
Art Unit(s)
3726
Total Applications
2343
Issued Applications
1904
Pending Applications
53
Abandoned Applications
396

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7813746 [patent_doc_number] => 20120060366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'METHOD FOR DETERMINING WIRING PATHWAY OF WIRING BOARD AND METHOD FOR DETERMINING WIRING PATHWAY OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/029972 [patent_app_country] => US [patent_app_date] => 2011-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8187 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20120060366.pdf [firstpage_image] =>[orig_patent_app_number] => 13029972 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/029972
METHOD FOR DETERMINING WIRING PATHWAY OF WIRING BOARD AND METHOD FOR DETERMINING WIRING PATHWAY OF SEMICONDUCTOR DEVICE Feb 16, 2011 Abandoned
Array ( [id] => 8507043 [patent_doc_number] => 20120306451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'SECONDARY CELL PROTECTION CIRCUIT AND BATTERY' [patent_app_type] => utility [patent_app_number] => 13/578781 [patent_app_country] => US [patent_app_date] => 2011-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7332 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13578781 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/578781
Secondary cell protection circuit and battery Feb 14, 2011 Issued
Array ( [id] => 8849438 [patent_doc_number] => 08458638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-04 [patent_title] => 'Cell library, integrated circuit, and methods of making same' [patent_app_type] => utility [patent_app_number] => 13/023172 [patent_app_country] => US [patent_app_date] => 2011-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3382 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13023172 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/023172
Cell library, integrated circuit, and methods of making same Feb 7, 2011 Issued
Array ( [id] => 7495209 [patent_doc_number] => 08032846 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-10-04 [patent_title] => 'Efficient provisioning of resources in public infrastructure for electronic design automation (EDA) tasks' [patent_app_type] => utility [patent_app_number] => 13/016712 [patent_app_country] => US [patent_app_date] => 2011-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6947 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/032/08032846.pdf [firstpage_image] =>[orig_patent_app_number] => 13016712 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/016712
Efficient provisioning of resources in public infrastructure for electronic design automation (EDA) tasks Jan 27, 2011 Issued
Array ( [id] => 9555841 [patent_doc_number] => 08762914 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-24 [patent_title] => 'Methods, systems, and articles of manufacture for constraint verification for implementing electronic circuit designs with electrical awareness' [patent_app_type] => utility [patent_app_number] => 12/982732 [patent_app_country] => US [patent_app_date] => 2010-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6245 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12982732 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/982732
Methods, systems, and articles of manufacture for constraint verification for implementing electronic circuit designs with electrical awareness Dec 29, 2010 Issued
Array ( [id] => 8985276 [patent_doc_number] => 08516406 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-08-20 [patent_title] => 'Methods, systems, and articles of manufacture for smart pattern capturing and layout fixing' [patent_app_type] => utility [patent_app_number] => 12/982712 [patent_app_country] => US [patent_app_date] => 2010-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 16 [patent_no_of_words] => 14084 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12982712 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/982712
Methods, systems, and articles of manufacture for smart pattern capturing and layout fixing Dec 29, 2010 Issued
Array ( [id] => 8655580 [patent_doc_number] => 08375348 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-02-12 [patent_title] => 'Method, system, and program product to implement colored tiles for detail routing for double pattern lithography' [patent_app_type] => utility [patent_app_number] => 12/981062 [patent_app_country] => US [patent_app_date] => 2010-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8686 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12981062 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/981062
Method, system, and program product to implement colored tiles for detail routing for double pattern lithography Dec 28, 2010 Issued
Array ( [id] => 11249912 [patent_doc_number] => 09475400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-25 [patent_title] => 'Charging device and methods for controlling a charging device' [patent_app_type] => utility [patent_app_number] => 13/992525 [patent_app_country] => US [patent_app_date] => 2010-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5734 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13992525 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/992525
Charging device and methods for controlling a charging device Dec 9, 2010 Issued
Array ( [id] => 8985270 [patent_doc_number] => 08516400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'Method for predicting tolerable spacing between conductors in semiconductor process' [patent_app_type] => utility [patent_app_number] => 12/941652 [patent_app_country] => US [patent_app_date] => 2010-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3156 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12941652 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/941652
Method for predicting tolerable spacing between conductors in semiconductor process Nov 7, 2010 Issued
Array ( [id] => 8172537 [patent_doc_number] => 20120107969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'METHOD AND SYSTEM FOR COMPARING LITHOGRAPHIC PROCESSING CONDITIONS AND OR DATA PREPARATION PROCESSES' [patent_app_type] => utility [patent_app_number] => 12/914212 [patent_app_country] => US [patent_app_date] => 2010-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7574 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20120107969.pdf [firstpage_image] =>[orig_patent_app_number] => 12914212 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/914212
Method and system for comparing lithographic processing conditions and or data preparation processes Oct 27, 2010 Issued
Array ( [id] => 7756712 [patent_doc_number] => 08112736 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-07 [patent_title] => 'Differential voltage defectivity monitoring method' [patent_app_type] => utility [patent_app_number] => 12/896869 [patent_app_country] => US [patent_app_date] => 2010-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 6909 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/112/08112736.pdf [firstpage_image] =>[orig_patent_app_number] => 12896869 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/896869
Differential voltage defectivity monitoring method Oct 1, 2010 Issued
Array ( [id] => 5989420 [patent_doc_number] => 20110012260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-20 [patent_title] => 'METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT, DESIGNING APPARATUS, SEMICONDUCTOR INTEGRATED CIRCUIT SYSTEM, SEMICONDUCTOR INTEGRATED CIRCUIT MOUNTING SUBSTRATE, PACKAGE AND SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/892273 [patent_app_country] => US [patent_app_date] => 2010-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 20960 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20110012260.pdf [firstpage_image] =>[orig_patent_app_number] => 12892273 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/892273
METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT, DESIGNING APPARATUS, SEMICONDUCTOR INTEGRATED CIRCUIT SYSTEM, SEMICONDUCTOR INTEGRATED CIRCUIT MOUNTING SUBSTRATE, PACKAGE AND SEMICONDUCTOR INTEGRATED CIRCUIT Sep 27, 2010 Abandoned
Array ( [id] => 7819910 [patent_doc_number] => 20120066530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'Configurable Power Switch Cells and Methodology' [patent_app_type] => utility [patent_app_number] => 12/879772 [patent_app_country] => US [patent_app_date] => 2010-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10262 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20120066530.pdf [firstpage_image] =>[orig_patent_app_number] => 12879772 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/879772
Configurable power switch cells and methodology Sep 9, 2010 Issued
Array ( [id] => 8438331 [patent_doc_number] => 08286116 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-10-09 [patent_title] => 'Composite wire indexing for programmable logic devices' [patent_app_type] => utility [patent_app_number] => 12/871764 [patent_app_country] => US [patent_app_date] => 2010-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6855 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12871764 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/871764
Composite wire indexing for programmable logic devices Aug 29, 2010 Issued
Array ( [id] => 8262256 [patent_doc_number] => 20120161677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-28 [patent_title] => 'BATTERY MODULE, BATTERY SYSTEM AND ELECTRICALLY DRIVEN VEHICLE' [patent_app_type] => utility [patent_app_number] => 13/393527 [patent_app_country] => US [patent_app_date] => 2010-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 23706 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13393527 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/393527
BATTERY MODULE, BATTERY SYSTEM AND ELECTRICALLY DRIVEN VEHICLE Aug 26, 2010 Abandoned
Array ( [id] => 7785219 [patent_doc_number] => 20120046775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-23 [patent_title] => 'METHOD FOR ENHANCING WAFER EXPOSURE EFFECTIVENESS AND EFFICIENCY' [patent_app_type] => utility [patent_app_number] => 12/860572 [patent_app_country] => US [patent_app_date] => 2010-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5091 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20120046775.pdf [firstpage_image] =>[orig_patent_app_number] => 12860572 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/860572
Method for enhancing wafer exposure effectiveness and efficiency Aug 19, 2010 Issued
Array ( [id] => 8595016 [patent_doc_number] => 08352899 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-01-08 [patent_title] => 'Method to modify an integrated circuit (IC) design' [patent_app_type] => utility [patent_app_number] => 12/860662 [patent_app_country] => US [patent_app_date] => 2010-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5139 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12860662 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/860662
Method to modify an integrated circuit (IC) design Aug 19, 2010 Issued
Array ( [id] => 8805029 [patent_doc_number] => 08443313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-14 [patent_title] => 'Circuit design optimization' [patent_app_type] => utility [patent_app_number] => 12/858522 [patent_app_country] => US [patent_app_date] => 2010-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8398 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12858522 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/858522
Circuit design optimization Aug 17, 2010 Issued
Array ( [id] => 8763383 [patent_doc_number] => 08423922 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-16 [patent_title] => 'Photomask designing method and photomask designing program' [patent_app_type] => utility [patent_app_number] => 12/850082 [patent_app_country] => US [patent_app_date] => 2010-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6596 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12850082 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/850082
Photomask designing method and photomask designing program Aug 3, 2010 Issued
Array ( [id] => 8752273 [patent_doc_number] => 08418117 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-09 [patent_title] => 'Chip-level ECO shrink' [patent_app_type] => utility [patent_app_number] => 12/831982 [patent_app_country] => US [patent_app_date] => 2010-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 3858 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12831982 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/831982
Chip-level ECO shrink Jul 6, 2010 Issued
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