John C. Hong

Array ( [id] => 8881396 [patent_doc_number] => 20130154580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-20 [patent_title] => 'APPARATUS FOR CHARGING THIN-FILM CAPACITORS' [patent_app_type] => utility [patent_app_number] => 13/807900 [patent_app_country] => US [patent_app_date] => 2010-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1421 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13807900 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8561938 [patent_doc_number] => 08336009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-18 [patent_title] => 'Method and apparatus for electronic system function verification at two levels' [patent_app_type] => utility [patent_app_number] => 12/827012 [patent_app_country] => US [patent_app_date] => 2010-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10402 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12827012 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8558316 [patent_doc_number] => 08332803 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-12-11 [patent_title] => 'Method and apparatus for integrated circuit package thermo-mechanical reliability analysis' [patent_app_type] => utility [patent_app_number] => 12/824542 [patent_app_country] => US [patent_app_date] => 2010-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4039 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12824542 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7563102 [patent_doc_number] => 20110276936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-10 [patent_title] => 'METHOD FOR ANALOG PLACEMENT AND GLOBAL ROUTING CONSIDERING WIRING SYMMETRY' [patent_app_type] => utility [patent_app_number] => 12/824942 [patent_app_country] => US [patent_app_date] => 2010-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3317 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20110276936.pdf [firstpage_image] =>[orig_patent_app_number] => 12824942 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8536246 [patent_doc_number] => 08312412 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-13 [patent_title] => 'Support apparatus and design support method' [patent_app_type] => utility [patent_app_number] => 12/825112 [patent_app_country] => US [patent_app_date] => 2010-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3704 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12825112 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8849430 [patent_doc_number] => 08458630 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-06-04 [patent_title] => 'Supporting dynamic aspects of polymorphism in high-level synthesis of integrated circuit designs' [patent_app_type] => utility [patent_app_number] => 12/824152 [patent_app_country] => US [patent_app_date] => 2010-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 8689 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12824152 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8461029 [patent_doc_number] => 08296715 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-23 [patent_title] => 'Wiring design assisting apparatus, wiring design assisting method, and computer-readable information recording medium' [patent_app_type] => utility [patent_app_number] => 12/823222 [patent_app_country] => US [patent_app_date] => 2010-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 30 [patent_no_of_words] => 17593 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12823222 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8655576 [patent_doc_number] => 08375344 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-02-12 [patent_title] => 'Method and system for determining configurations' [patent_app_type] => utility [patent_app_number] => 12/824042 [patent_app_country] => US [patent_app_date] => 2010-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7770 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12824042 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7671723 [patent_doc_number] => 20110320992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'BUFFER-AWARE ROUTING IN INTEGRATED CIRCUIT DESIGN' [patent_app_type] => utility [patent_app_number] => 12/823232 [patent_app_country] => US [patent_app_date] => 2010-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9853 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12823232 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7671728 [patent_doc_number] => 20110320997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'Delay-Cell Footprint-Compatible Buffers' [patent_app_type] => utility [patent_app_number] => 12/822272 [patent_app_country] => US [patent_app_date] => 2010-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2130 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12822272 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8343242 [patent_doc_number] => 08245181 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-14 [patent_title] => 'Printed circuit board layout system and method thereof' [patent_app_type] => utility [patent_app_number] => 12/813522 [patent_app_country] => US [patent_app_date] => 2010-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1969 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12813522 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6006215 [patent_doc_number] => 20110119544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-19 [patent_title] => 'User Guided Short Correction And Schematic Fix Visualization' [patent_app_type] => utility [patent_app_number] => 12/797602 [patent_app_country] => US [patent_app_date] => 2010-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10655 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20110119544.pdf [firstpage_image] =>[orig_patent_app_number] => 12797602 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7653277 [patent_doc_number] => 20110302546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-08 [patent_title] => 'METHOD AND APPARATUS FOR PERFORMING SCENARIO REDUCTION' [patent_app_type] => utility [patent_app_number] => 12/795592 [patent_app_country] => US [patent_app_date] => 2010-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11695 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0302/20110302546.pdf [firstpage_image] =>[orig_patent_app_number] => 12795592 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6474992 [patent_doc_number] => 20100207655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-19 [patent_title] => 'Method and Apparatus for Small Die Low Power System-on-chip Design with Intelligent Power Supply Chip' [patent_app_type] => utility [patent_app_number] => 12/772803 [patent_app_country] => US [patent_app_date] => 2010-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3109 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20100207655.pdf [firstpage_image] =>[orig_patent_app_number] => 12772803 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7682406 [patent_doc_number] => 20100242005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-23 [patent_title] => 'System and method for design, procurement and manufacturing collaboration' [patent_app_type] => utility [patent_app_number] => 12/799534 [patent_app_country] => US [patent_app_date] => 2010-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7286 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20100242005.pdf [firstpage_image] =>[orig_patent_app_number] => 12799534 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8449288 [patent_doc_number] => 08291358 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-16 [patent_title] => 'Synchronous to asynchronous logic conversion' [patent_app_type] => utility [patent_app_number] => 12/768129 [patent_app_country] => US [patent_app_date] => 2010-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4912 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12768129 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8220458 [patent_doc_number] => 08196087 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-05 [patent_title] => 'Chip area optimized pads' [patent_app_type] => utility [patent_app_number] => 12/760442 [patent_app_country] => US [patent_app_date] => 2010-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2661 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/196/08196087.pdf [firstpage_image] =>[orig_patent_app_number] => 12760442 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9218558 [patent_doc_number] => 08631368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-14 [patent_title] => 'Method and circuit to generate race condition test data at multiple supply voltages' [patent_app_type] => utility [patent_app_number] => 12/749602 [patent_app_country] => US [patent_app_date] => 2010-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 14429 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12749602 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8391236 [patent_doc_number] => 20120229084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-13 [patent_title] => 'SYSTEM AND METHOD FOR COMPATIBLE WIRED CHARGING AND WIRELESS CHARGING' [patent_app_type] => utility [patent_app_number] => 13/509961 [patent_app_country] => US [patent_app_date] => 2010-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3460 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13509961 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6396181 [patent_doc_number] => 20100164560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS ELECTRONIC APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/721776 [patent_app_country] => US [patent_app_date] => 2010-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10977 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20100164560.pdf [firstpage_image] =>[orig_patent_app_number] => 12721776 [rel_patent_id] =>[rel_patent_doc_number] =>)