Search

John C. Hong

Examiner (ID: 1779, Phone: (571)272-4529 , Office: P/3726 )

Most Active Art Unit
3726
Art Unit(s)
3726
Total Applications
2343
Issued Applications
1904
Pending Applications
53
Abandoned Applications
396

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9103 [patent_doc_number] => 07818694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-19 [patent_title] => 'IC layout optimization to improve yield' [patent_app_type] => utility [patent_app_number] => 12/342353 [patent_app_country] => US [patent_app_date] => 2008-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 5012 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/818/07818694.pdf [firstpage_image] =>[orig_patent_app_number] => 12342353 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/342353
IC layout optimization to improve yield Dec 22, 2008 Issued
Array ( [id] => 5547485 [patent_doc_number] => 20090157362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'MODEL MODIFICATION METHOD FOR A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/336212 [patent_app_country] => US [patent_app_date] => 2008-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3111 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20090157362.pdf [firstpage_image] =>[orig_patent_app_number] => 12336212 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/336212
MODEL MODIFICATION METHOD FOR A SEMICONDUCTOR DEVICE Dec 15, 2008 Abandoned
Array ( [id] => 8655575 [patent_doc_number] => 08375343 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-02-12 [patent_title] => 'Methods and apparatus for waveform based variational static timing analysis' [patent_app_type] => utility [patent_app_number] => 12/331172 [patent_app_country] => US [patent_app_date] => 2008-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 13009 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12331172 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/331172
Methods and apparatus for waveform based variational static timing analysis Dec 8, 2008 Issued
Array ( [id] => 4642103 [patent_doc_number] => 08020139 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-09-13 [patent_title] => 'Method and apparatus for implementing a dataflow circuit model using application-specific memory implementations' [patent_app_type] => utility [patent_app_number] => 12/331212 [patent_app_country] => US [patent_app_date] => 2008-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4223 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/020/08020139.pdf [firstpage_image] =>[orig_patent_app_number] => 12331212 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/331212
Method and apparatus for implementing a dataflow circuit model using application-specific memory implementations Dec 8, 2008 Issued
Array ( [id] => 8343232 [patent_doc_number] => 08245165 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-08-14 [patent_title] => 'Methods and apparatus for waveform based variational static timing analysis' [patent_app_type] => utility [patent_app_number] => 12/331072 [patent_app_country] => US [patent_app_date] => 2008-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 12979 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12331072 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/331072
Methods and apparatus for waveform based variational static timing analysis Dec 8, 2008 Issued
Array ( [id] => 4443769 [patent_doc_number] => 07900171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-01 [patent_title] => 'Electronic stream processing circuit with locally controlled parameter updates, and method of designing such a circuit' [patent_app_type] => utility [patent_app_number] => 12/256334 [patent_app_country] => US [patent_app_date] => 2008-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5164 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/900/07900171.pdf [firstpage_image] =>[orig_patent_app_number] => 12256334 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/256334
Electronic stream processing circuit with locally controlled parameter updates, and method of designing such a circuit Oct 21, 2008 Issued
Array ( [id] => 5418268 [patent_doc_number] => 20090044155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-12 [patent_title] => 'METHOD AND SYSTEM FOR DESIGNING AN ELECTRONIC CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/255819 [patent_app_country] => US [patent_app_date] => 2008-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7030 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20090044155.pdf [firstpage_image] =>[orig_patent_app_number] => 12255819 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/255819
Method and system for designing an electronic circuit Oct 21, 2008 Issued
Array ( [id] => 28603 [patent_doc_number] => 07797666 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-09-14 [patent_title] => 'Systems and methods for mapping arbitrary logic functions into synchronous embedded memories' [patent_app_type] => utility [patent_app_number] => 12/244635 [patent_app_country] => US [patent_app_date] => 2008-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 3466 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/797/07797666.pdf [firstpage_image] =>[orig_patent_app_number] => 12244635 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/244635
Systems and methods for mapping arbitrary logic functions into synchronous embedded memories Oct 1, 2008 Issued
Array ( [id] => 8331722 [patent_doc_number] => 08239798 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-08-07 [patent_title] => 'Methods, systems, and apparatus for variation aware extracted timing models' [patent_app_type] => utility [patent_app_number] => 12/185072 [patent_app_country] => US [patent_app_date] => 2008-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 15243 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12185072 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/185072
Methods, systems, and apparatus for variation aware extracted timing models Aug 1, 2008 Issued
Array ( [id] => 4441502 [patent_doc_number] => 07971177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Design tool for charge trapping memory using simulated programming operations' [patent_app_type] => utility [patent_app_number] => 12/182352 [patent_app_country] => US [patent_app_date] => 2008-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 5807 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/971/07971177.pdf [firstpage_image] =>[orig_patent_app_number] => 12182352 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/182352
Design tool for charge trapping memory using simulated programming operations Jul 29, 2008 Issued
Array ( [id] => 7726422 [patent_doc_number] => 08099702 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-17 [patent_title] => 'Method and apparatus for proximate placement of sequential cells' [patent_app_type] => utility [patent_app_number] => 12/182442 [patent_app_country] => US [patent_app_date] => 2008-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8794 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/099/08099702.pdf [firstpage_image] =>[orig_patent_app_number] => 12182442 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/182442
Method and apparatus for proximate placement of sequential cells Jul 29, 2008 Issued
Array ( [id] => 7813517 [patent_doc_number] => 08136055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-13 [patent_title] => 'Systems for real-time contamination, environmental, or physical monitoring of a photomask' [patent_app_type] => utility [patent_app_number] => 12/182672 [patent_app_country] => US [patent_app_date] => 2008-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5629 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/136/08136055.pdf [firstpage_image] =>[orig_patent_app_number] => 12182672 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/182672
Systems for real-time contamination, environmental, or physical monitoring of a photomask Jul 29, 2008 Issued
Array ( [id] => 5504269 [patent_doc_number] => 20090164957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-25 [patent_title] => 'Design Structure for Glitchless Clock Multiplexer Optimized for Synchronous and Asynchronous Clocks' [patent_app_type] => utility [patent_app_number] => 12/174572 [patent_app_country] => US [patent_app_date] => 2008-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8206 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20090164957.pdf [firstpage_image] =>[orig_patent_app_number] => 12174572 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/174572
Structure for glitchless clock multiplexer optimized for synchronous and asynchronous clocks Jul 15, 2008 Issued
Array ( [id] => 7542996 [patent_doc_number] => 08060845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-15 [patent_title] => 'Minimizing impact of design changes for integrated circuit designs' [patent_app_type] => utility [patent_app_number] => 12/173222 [patent_app_country] => US [patent_app_date] => 2008-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2651 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/060/08060845.pdf [firstpage_image] =>[orig_patent_app_number] => 12173222 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/173222
Minimizing impact of design changes for integrated circuit designs Jul 14, 2008 Issued
Array ( [id] => 288684 [patent_doc_number] => 07552413 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-23 [patent_title] => 'System and computer program for verifying performance of an array by simulating operation of edge cells in a full array model' [patent_app_type] => utility [patent_app_number] => 12/166811 [patent_app_country] => US [patent_app_date] => 2008-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3774 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/552/07552413.pdf [firstpage_image] =>[orig_patent_app_number] => 12166811 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/166811
System and computer program for verifying performance of an array by simulating operation of edge cells in a full array model Jul 1, 2008 Issued
Array ( [id] => 4637062 [patent_doc_number] => 08015527 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-06 [patent_title] => 'Routing of wires of an electronic circuit' [patent_app_type] => utility [patent_app_number] => 12/166012 [patent_app_country] => US [patent_app_date] => 2008-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5848 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/015/08015527.pdf [firstpage_image] =>[orig_patent_app_number] => 12166012 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/166012
Routing of wires of an electronic circuit Jun 30, 2008 Issued
Array ( [id] => 4621761 [patent_doc_number] => 08001492 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-16 [patent_title] => 'Evaluation method for interconnects interacted with integrated-circuit manufacture' [patent_app_type] => utility [patent_app_number] => 12/215552 [patent_app_country] => US [patent_app_date] => 2008-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 5362 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/001/08001492.pdf [firstpage_image] =>[orig_patent_app_number] => 12215552 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/215552
Evaluation method for interconnects interacted with integrated-circuit manufacture Jun 26, 2008 Issued
Array ( [id] => 4684140 [patent_doc_number] => 20080250366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-09 [patent_title] => 'NOISE CHECKING METHOD AND APPARATUS, AND COMPUTER-READABLE RECORDING MEDIUM IN WHICH NOISE CHECKING PROGRAM IS STORED' [patent_app_type] => utility [patent_app_number] => 12/141392 [patent_app_country] => US [patent_app_date] => 2008-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 17727 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20080250366.pdf [firstpage_image] =>[orig_patent_app_number] => 12141392 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/141392
Noise checking method and apparatus, and computer-readable recording medium in which noise checking program is stored Jun 17, 2008 Issued
Array ( [id] => 7548061 [patent_doc_number] => 08056042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-08 [patent_title] => 'Automatic delay adjusting method for semiconductor integrated circuit by using dummy wiring' [patent_app_type] => utility [patent_app_number] => 12/213372 [patent_app_country] => US [patent_app_date] => 2008-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 33 [patent_no_of_words] => 5729 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/056/08056042.pdf [firstpage_image] =>[orig_patent_app_number] => 12213372 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/213372
Automatic delay adjusting method for semiconductor integrated circuit by using dummy wiring Jun 17, 2008 Issued
Array ( [id] => 4712280 [patent_doc_number] => 20080300806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'Power consumption calculating method' [patent_app_type] => utility [patent_app_number] => 12/155082 [patent_app_country] => US [patent_app_date] => 2008-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7132 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0300/20080300806.pdf [firstpage_image] =>[orig_patent_app_number] => 12155082 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/155082
Power consumption calculating method May 28, 2008 Abandoned
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