Search

John C. Hong

Examiner (ID: 1779, Phone: (571)272-4529 , Office: P/3726 )

Most Active Art Unit
3726
Art Unit(s)
3726
Total Applications
2343
Issued Applications
1904
Pending Applications
53
Abandoned Applications
396

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5491437 [patent_doc_number] => 20090292508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-26 [patent_title] => 'METHOD AND APPARATUS FOR MODELING LONG RANGE EUVL FLARE' [patent_app_type] => utility [patent_app_number] => 12/126152 [patent_app_country] => US [patent_app_date] => 2008-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5810 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0292/20090292508.pdf [firstpage_image] =>[orig_patent_app_number] => 12126152 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/126152
Method and apparatus for modeling long-range EUVL flare May 22, 2008 Issued
Array ( [id] => 4443782 [patent_doc_number] => 07900174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-01 [patent_title] => 'Method and system for characterizing an integrated circuit design' [patent_app_type] => utility [patent_app_number] => 12/152932 [patent_app_country] => US [patent_app_date] => 2008-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6752 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/900/07900174.pdf [firstpage_image] =>[orig_patent_app_number] => 12152932 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/152932
Method and system for characterizing an integrated circuit design May 18, 2008 Issued
Array ( [id] => 4841724 [patent_doc_number] => 20080282210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-13 [patent_title] => 'System And Method For Product Yield Prediction' [patent_app_type] => utility [patent_app_number] => 12/119862 [patent_app_country] => US [patent_app_date] => 2008-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8435 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20080282210.pdf [firstpage_image] =>[orig_patent_app_number] => 12119862 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/119862
System and method for product yield prediction May 12, 2008 Issued
Array ( [id] => 9940925 [patent_doc_number] => 08990757 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-24 [patent_title] => 'Dedicated interface architecture for a hybrid integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/114143 [patent_app_country] => US [patent_app_date] => 2008-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 3827 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12114143 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/114143
Dedicated interface architecture for a hybrid integrated circuit May 1, 2008 Issued
Array ( [id] => 4582577 [patent_doc_number] => 07840930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-23 [patent_title] => 'Signal connection program, method, and device of hierarchical logic circuit' [patent_app_type] => utility [patent_app_number] => 12/102462 [patent_app_country] => US [patent_app_date] => 2008-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 38 [patent_no_of_words] => 9210 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/840/07840930.pdf [firstpage_image] =>[orig_patent_app_number] => 12102462 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/102462
Signal connection program, method, and device of hierarchical logic circuit Apr 13, 2008 Issued
Array ( [id] => 4815358 [patent_doc_number] => 20080195989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'CONTENT BASED YIELD PREDICTION OF VLSI DESIGNS' [patent_app_type] => utility [patent_app_number] => 12/101599 [patent_app_country] => US [patent_app_date] => 2008-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2914 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20080195989.pdf [firstpage_image] =>[orig_patent_app_number] => 12101599 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/101599
Content based yield prediction of VLSI designs Apr 10, 2008 Issued
Array ( [id] => 6234631 [patent_doc_number] => 20100185996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-22 [patent_title] => 'SEMICONDUCTOR LAYOUT SCANNING METHOD AND SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/593392 [patent_app_country] => US [patent_app_date] => 2008-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4355 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20100185996.pdf [firstpage_image] =>[orig_patent_app_number] => 12593392 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/593392
Semiconductor layout scanning method and system Mar 18, 2008 Issued
Array ( [id] => 5535427 [patent_doc_number] => 20090235215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-17 [patent_title] => 'GRIDDED GLYPH GEOMETRIC OBJECTS (L3GO) DESIGN METHOD' [patent_app_type] => utility [patent_app_number] => 12/047566 [patent_app_country] => US [patent_app_date] => 2008-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3308 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20090235215.pdf [firstpage_image] =>[orig_patent_app_number] => 12047566 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/047566
Gridded glyph geometric objects (L3GO) design method Mar 12, 2008 Issued
Array ( [id] => 4700403 [patent_doc_number] => 20080222587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'Integrated Circuit Cell Library for Multiple Patterning' [patent_app_type] => utility [patent_app_number] => 12/041584 [patent_app_country] => US [patent_app_date] => 2008-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9508 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20080222587.pdf [firstpage_image] =>[orig_patent_app_number] => 12041584 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/041584
Integrated circuit cell library for multiple patterning Mar 2, 2008 Issued
Array ( [id] => 4602990 [patent_doc_number] => 07979835 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-07-12 [patent_title] => 'Method of estimating resource requirements for a circuit design' [patent_app_type] => utility [patent_app_number] => 12/041182 [patent_app_country] => US [patent_app_date] => 2008-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 11306 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/979/07979835.pdf [firstpage_image] =>[orig_patent_app_number] => 12041182 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/041182
Method of estimating resource requirements for a circuit design Mar 2, 2008 Issued
Array ( [id] => 5393529 [patent_doc_number] => 20090210842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'Automated Method for Buffering in a VLSI Design' [patent_app_type] => utility [patent_app_number] => 12/032762 [patent_app_country] => US [patent_app_date] => 2008-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6624 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20090210842.pdf [firstpage_image] =>[orig_patent_app_number] => 12032762 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/032762
Automated method for buffering in a VLSI design Feb 17, 2008 Issued
Array ( [id] => 5393527 [patent_doc_number] => 20090210840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'Optimization Method of Integrated Circuit Design for Reduction of Global Clock Load and Balancing Clock Skew' [patent_app_type] => utility [patent_app_number] => 12/032542 [patent_app_country] => US [patent_app_date] => 2008-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4589 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20090210840.pdf [firstpage_image] =>[orig_patent_app_number] => 12032542 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/032542
Optimization method of integrated circuit design for reduction of global clock load and balancing clock skew Feb 14, 2008 Issued
Array ( [id] => 4724864 [patent_doc_number] => 20080204405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'Method and System of Displaying an Exposure Condition' [patent_app_type] => utility [patent_app_number] => 12/031782 [patent_app_country] => US [patent_app_date] => 2008-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4531 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20080204405.pdf [firstpage_image] =>[orig_patent_app_number] => 12031782 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/031782
Method and system of displaying an exposure condition Feb 14, 2008 Issued
Array ( [id] => 5393534 [patent_doc_number] => 20090210847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'SYNCHRONOUS TO ASYNCHRONOUS LOGIC CONVERSION' [patent_app_type] => utility [patent_app_number] => 12/031992 [patent_app_country] => US [patent_app_date] => 2008-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4769 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20090210847.pdf [firstpage_image] =>[orig_patent_app_number] => 12031992 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/031992
Synchronous to asynchronous logic conversion Feb 14, 2008 Issued
Array ( [id] => 4730894 [patent_doc_number] => 20080209366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'METHOD AND APPARATUS FOR ANALYZING CIRCUIT MODEL BY REDUCTION AND COMPUTER PROGRAM PRODUCT FOR ANALYZING THE CIRCUIT MODEL' [patent_app_type] => utility [patent_app_number] => 12/027732 [patent_app_country] => US [patent_app_date] => 2008-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5642 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20080209366.pdf [firstpage_image] =>[orig_patent_app_number] => 12027732 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/027732
Method and apparatus for analyzing circuit model by reduction and computer program product for analyzing the circuit model Feb 6, 2008 Issued
Array ( [id] => 4787654 [patent_doc_number] => 20080140983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'AFFINITY-BASED CLUSTERING OF VECTORS FOR PARTITIONING THE COLUMNS OF A MATRIX' [patent_app_type] => utility [patent_app_number] => 12/020879 [patent_app_country] => US [patent_app_date] => 2008-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7994 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20080140983.pdf [firstpage_image] =>[orig_patent_app_number] => 12020879 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/020879
Affinity-based clustering of vectors for partitioning the columns of a matrix Jan 27, 2008 Issued
Array ( [id] => 7595653 [patent_doc_number] => 07620929 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-11-17 [patent_title] => 'Programmable logic device having a programmable selector circuit' [patent_app_type] => utility [patent_app_number] => 12/020712 [patent_app_country] => US [patent_app_date] => 2008-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5835 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/620/07620929.pdf [firstpage_image] =>[orig_patent_app_number] => 12020712 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/020712
Programmable logic device having a programmable selector circuit Jan 27, 2008 Issued
Array ( [id] => 4602989 [patent_doc_number] => 07979834 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-07-12 [patent_title] => 'Predicting timing degradations for data signals in an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/018992 [patent_app_country] => US [patent_app_date] => 2008-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 19427 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/979/07979834.pdf [firstpage_image] =>[orig_patent_app_number] => 12018992 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/018992
Predicting timing degradations for data signals in an integrated circuit Jan 23, 2008 Issued
Array ( [id] => 4500841 [patent_doc_number] => 07904865 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-08 [patent_title] => 'Placement driven routing' [patent_app_type] => utility [patent_app_number] => 12/018422 [patent_app_country] => US [patent_app_date] => 2008-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4256 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/904/07904865.pdf [firstpage_image] =>[orig_patent_app_number] => 12018422 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/018422
Placement driven routing Jan 22, 2008 Issued
Array ( [id] => 5354939 [patent_doc_number] => 20090186283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-23 [patent_title] => 'Photomasks and Methods Of Forming Photomasks' [patent_app_type] => utility [patent_app_number] => 12/018612 [patent_app_country] => US [patent_app_date] => 2008-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4928 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20090186283.pdf [firstpage_image] =>[orig_patent_app_number] => 12018612 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/018612
Methods of forming photomasks Jan 22, 2008 Issued
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