
John C. Hong
Examiner (ID: 1779, Phone: (571)272-4529 , Office: P/3726 )
| Most Active Art Unit | 3726 |
| Art Unit(s) | 3726 |
| Total Applications | 2343 |
| Issued Applications | 1904 |
| Pending Applications | 53 |
| Abandoned Applications | 396 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5582814
[patent_doc_number] => 20090102016
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-23
[patent_title] => 'DESIGN STRUCTURE INCORPORATING VERTICAL PARALLEL PLATE CAPACITOR STRUCTURES'
[patent_app_type] => utility
[patent_app_number] => 11/876402
[patent_app_country] => US
[patent_app_date] => 2007-10-22
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0102/20090102016.pdf
[firstpage_image] =>[orig_patent_app_number] => 11876402
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/876402 | DESIGN STRUCTURE INCORPORATING VERTICAL PARALLEL PLATE CAPACITOR STRUCTURES | Oct 21, 2007 | Abandoned |
Array
(
[id] => 5587522
[patent_doc_number] => 20090106724
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-23
[patent_title] => 'Transition Balancing For Noise Reduction/Di/Dt Reduction During Design, Synthesis, and Physical Design'
[patent_app_type] => utility
[patent_app_number] => 11/875032
[patent_app_country] => US
[patent_app_date] => 2007-10-19
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0106/20090106724.pdf
[firstpage_image] =>[orig_patent_app_number] => 11875032
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/875032 | Transition balancing for noise reduction/Di/Dt reduction during design, synthesis, and physical design | Oct 18, 2007 | Issued |
Array
(
[id] => 7706531
[patent_doc_number] => 08091053
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-01-03
[patent_title] => 'System, method, and program for generating circuit'
[patent_app_type] => utility
[patent_app_number] => 11/907712
[patent_app_country] => US
[patent_app_date] => 2007-10-16
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[pdf_file] => patents/08/091/08091053.pdf
[firstpage_image] =>[orig_patent_app_number] => 11907712
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/907712 | System, method, and program for generating circuit | Oct 15, 2007 | Issued |
Array
(
[id] => 5286718
[patent_doc_number] => 20090100393
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-16
[patent_title] => 'METHOD AND APPARATUS FOR INCREMENTALLY COMPUTING CRITICALITY AND YIELD GRADIENT'
[patent_app_type] => utility
[patent_app_number] => 11/870672
[patent_app_country] => US
[patent_app_date] => 2007-10-11
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/870672 | Method and apparatus for incrementally computing criticality and yield gradient | Oct 10, 2007 | Issued |
Array
(
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[patent_issue_date] => 2009-04-09
[patent_title] => 'Validation Of An Integrated Circuit For Electro Static Discharge Compliance'
[patent_app_type] => utility
[patent_app_number] => 11/867012
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[firstpage_image] =>[orig_patent_app_number] => 11867012
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/867012 | Validation of an integrated circuit for electro static discharge compliance | Oct 3, 2007 | Issued |
Array
(
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[patent_title] => 'METHOD AND PROGRAM FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT'
[patent_app_type] => utility
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[firstpage_image] =>[orig_patent_app_number] => 11865242
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/865242 | Method and program for designing semiconductor integrated circuit | Sep 30, 2007 | Issued |
Array
(
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[patent_issue_date] => 2009-04-02
[patent_title] => 'Layout Quality Gauge for Integrated Circuit Design'
[patent_app_type] => utility
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[patent_app_country] => US
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[pdf_file] => publications/A1/0089/20090089726.pdf
[firstpage_image] =>[orig_patent_app_number] => 11865252
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/865252 | Layout quality gauge for integrated circuit design | Sep 30, 2007 | Issued |
Array
(
[id] => 5430415
[patent_doc_number] => 20090089725
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-02
[patent_title] => 'SYNTHESIS OF ASSERTIONS FROM STATEMENTS OF POWER INTENT'
[patent_app_type] => utility
[patent_app_number] => 11/863512
[patent_app_country] => US
[patent_app_date] => 2007-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => publications/A1/0089/20090089725.pdf
[firstpage_image] =>[orig_patent_app_number] => 11863512
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/863512 | Synthesis of assertions from statements of power intent | Sep 27, 2007 | Issued |
Array
(
[id] => 4755062
[patent_doc_number] => 20080163138
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-03
[patent_title] => 'POWER SUPPLY NOISE ANALYSIS MODEL GENERATING METHOD AND POWER SUPPLY NOISE ANALYSIS MODEL GENERATING APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 11/864122
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[pdf_file] => publications/A1/0163/20080163138.pdf
[firstpage_image] =>[orig_patent_app_number] => 11864122
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/864122 | Power supply noise analysis model generating method and power supply noise analysis model generating apparatus | Sep 27, 2007 | Issued |
Array
(
[id] => 5430419
[patent_doc_number] => 20090089729
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-02
[patent_title] => 'Distorted Waveform Propagation and Crosstalk Delay Analysis Using Multiple Cell Models'
[patent_app_type] => utility
[patent_app_number] => 11/863252
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/863252 | Distorted waveform propagation and crosstalk delay analysis using multiple cell models | Sep 27, 2007 | Issued |
Array
(
[id] => 5510476
[patent_doc_number] => 20090083683
[patent_country] => US
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[patent_title] => 'Method and Apparatus for Implementing Communication Between a Software Side and a Hardware Side of a Test Bench in a Transaction-Based Acceleration Verification System'
[patent_app_type] => utility
[patent_app_number] => 11/861952
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[firstpage_image] =>[orig_patent_app_number] => 11861952
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/861952 | Method and apparatus for implementing communication between a software side and a hardware side of a test bench in a transaction-based acceleration verification system | Sep 25, 2007 | Issued |
Array
(
[id] => 5508630
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[patent_title] => 'METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING AN EXTENDED STRESS LINER'
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[patent_app_number] => 11/861492
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[firstpage_image] =>[orig_patent_app_number] => 11861492
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/861492 | Method for fabricating a semiconductor device having an extended stress liner | Sep 25, 2007 | Issued |
Array
(
[id] => 4722866
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[patent_title] => 'METHOD FOR DESIGNING AND MANUFACTURING SEMICONDUCTOR DEVICE AND SOFTWARE THEREFOR'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/859162 | METHOD FOR DESIGNING AND MANUFACTURING SEMICONDUCTOR DEVICE AND SOFTWARE THEREFOR | Sep 20, 2007 | Abandoned |
Array
(
[id] => 180149
[patent_doc_number] => 07657865
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[patent_kind] => B2
[patent_issue_date] => 2010-02-02
[patent_title] => 'Computer-readable recording medium recording a mask data generation program, mask data generation method, mask fabrication method, exposure method, and device manufacturing method'
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Array
(
[id] => 4923878
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[patent_title] => 'Validation processing apparatus'
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Array
(
[id] => 5454694
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Array
(
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Array
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Array
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[patent_title] => 'METHOD AND APPARATUS FOR CHARACTERISTIC IMPEDANCE DISCONTINUITY REDUCTION IN HIGH-SPEED FLEXIBLE CIRCUIT APPLICATIONS'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/842533 | Method and apparatus for characteristics impedance discontinuity reduction in high-speed flexible circuit applications | Aug 20, 2007 | Issued |
Array
(
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[patent_title] => 'Optical proximity correction (OPC) processing method for preventing the occurrence of off-grid'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/841063 | Optical proximity correction (OPC) processing method for preventing the occurrence of off-grid | Aug 19, 2007 | Issued |