Search

John C. Hong

Examiner (ID: 1779, Phone: (571)272-4529 , Office: P/3726 )

Most Active Art Unit
3726
Art Unit(s)
3726
Total Applications
2343
Issued Applications
1904
Pending Applications
53
Abandoned Applications
396

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7591321 [patent_doc_number] => 07653886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-26 [patent_title] => 'Crosslinking of netlists' [patent_app_type] => utility [patent_app_number] => 11/840122 [patent_app_country] => US [patent_app_date] => 2007-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5369 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/653/07653886.pdf [firstpage_image] =>[orig_patent_app_number] => 11840122 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/840122
Crosslinking of netlists Aug 15, 2007 Issued
Array ( [id] => 4747497 [patent_doc_number] => 20080092099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'ANALOG AND MIXED SIGNAL IC LAYOUT SYSTEM' [patent_app_type] => utility [patent_app_number] => 11/839042 [patent_app_country] => US [patent_app_date] => 2007-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8430 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20080092099.pdf [firstpage_image] =>[orig_patent_app_number] => 11839042 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/839042
Analog and mixed signal IC layout system Aug 14, 2007 Issued
Array ( [id] => 5444615 [patent_doc_number] => 20090045841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-19 [patent_title] => 'Method for Radiation Tolerance by Implant Well Notching' [patent_app_type] => utility [patent_app_number] => 11/838286 [patent_app_country] => US [patent_app_date] => 2007-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3471 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20090045841.pdf [firstpage_image] =>[orig_patent_app_number] => 11838286 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/838286
Method for radiation tolerance by implant well notching Aug 13, 2007 Issued
Array ( [id] => 137363 [patent_doc_number] => 07698682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-13 [patent_title] => 'Writing error verification method of pattern writing apparatus and generation apparatus of writing error verification data for pattern writing apparatus' [patent_app_type] => utility [patent_app_number] => 11/838542 [patent_app_country] => US [patent_app_date] => 2007-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 7808 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/698/07698682.pdf [firstpage_image] =>[orig_patent_app_number] => 11838542 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/838542
Writing error verification method of pattern writing apparatus and generation apparatus of writing error verification data for pattern writing apparatus Aug 13, 2007 Issued
Array ( [id] => 5444614 [patent_doc_number] => 20090045840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-19 [patent_title] => 'Method for Radiation Tolerance by Logic Book Folding' [patent_app_type] => utility [patent_app_number] => 11/838273 [patent_app_country] => US [patent_app_date] => 2007-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3379 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20090045840.pdf [firstpage_image] =>[orig_patent_app_number] => 11838273 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/838273
Method for radiation tolerance by logic book folding Aug 13, 2007 Issued
Array ( [id] => 136722 [patent_doc_number] => 07703069 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-04-20 [patent_title] => 'Three-dimensional mask model for photolithography simulation' [patent_app_type] => utility [patent_app_number] => 11/838582 [patent_app_country] => US [patent_app_date] => 2007-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7197 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/703/07703069.pdf [firstpage_image] =>[orig_patent_app_number] => 11838582 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/838582
Three-dimensional mask model for photolithography simulation Aug 13, 2007 Issued
Array ( [id] => 97622 [patent_doc_number] => 07739644 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-06-15 [patent_title] => 'Methods, systems, and computer program products for grid-morphing techniques in placement, floorplanning, and legalization' [patent_app_type] => utility [patent_app_number] => 11/838193 [patent_app_country] => US [patent_app_date] => 2007-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 5565 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/739/07739644.pdf [firstpage_image] =>[orig_patent_app_number] => 11838193 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/838193
Methods, systems, and computer program products for grid-morphing techniques in placement, floorplanning, and legalization Aug 12, 2007 Issued
Array ( [id] => 5086845 [patent_doc_number] => 20070276896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-29 [patent_title] => 'AFFINITY-BASED CLUSTERING OF VECTORS FOR PARTITIONING THE COLUMNS OF A MATRIX' [patent_app_type] => utility [patent_app_number] => 11/836842 [patent_app_country] => US [patent_app_date] => 2007-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7995 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20070276896.pdf [firstpage_image] =>[orig_patent_app_number] => 11836842 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/836842
Affinity-based clustering of vectors for partitioning the columns of a matrix Aug 9, 2007 Issued
Array ( [id] => 5363072 [patent_doc_number] => 20090037866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'ALTERNATING PHASE SHIFT MASK OPTIMIZATION FOR IMPROVED PROCESS WINDOW' [patent_app_type] => utility [patent_app_number] => 11/833462 [patent_app_country] => US [patent_app_date] => 2007-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4259 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20090037866.pdf [firstpage_image] =>[orig_patent_app_number] => 11833462 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/833462
ALTERNATING PHASE SHIFT MASK OPTIMIZATION FOR IMPROVED PROCESS WINDOW Aug 2, 2007 Abandoned
Array ( [id] => 4455162 [patent_doc_number] => 07966593 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-06-21 [patent_title] => 'Integrated circuit design system, method, and computer program product that takes into account the stability of various design signals' [patent_app_type] => utility [patent_app_number] => 11/832443 [patent_app_country] => US [patent_app_date] => 2007-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 5642 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/966/07966593.pdf [firstpage_image] =>[orig_patent_app_number] => 11832443 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/832443
Integrated circuit design system, method, and computer program product that takes into account the stability of various design signals Jul 31, 2007 Issued
Array ( [id] => 5363064 [patent_doc_number] => 20090037858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'Method For Automatic Maximization of Coverage in Constrained Stimulus Driven Simulation' [patent_app_type] => utility [patent_app_number] => 11/831673 [patent_app_country] => US [patent_app_date] => 2007-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10822 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20090037858.pdf [firstpage_image] =>[orig_patent_app_number] => 11831673 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/831673
Method for automatic maximization of coverage in constrained stimulus driven simulation Jul 30, 2007 Issued
Array ( [id] => 5363059 [patent_doc_number] => 20090037853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'ASYNCHRONOUS, MULTI-RAIL DIGITAL CIRCUIT WITH GATING AND GATED SUB-CIRCUITS AND METHOD FOR DESIGNING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/831942 [patent_app_country] => US [patent_app_date] => 2007-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4721 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20090037853.pdf [firstpage_image] =>[orig_patent_app_number] => 11831942 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/831942
Asynchronous, multi-rail digital circuit with gating and gated sub-circuits and method for designing the same Jul 30, 2007 Issued
Array ( [id] => 241486 [patent_doc_number] => 07594212 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-09-22 [patent_title] => 'Automatic pin placement for integrated circuits to aid circuit board design' [patent_app_type] => utility [patent_app_number] => 11/888162 [patent_app_country] => US [patent_app_date] => 2007-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6811 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/594/07594212.pdf [firstpage_image] =>[orig_patent_app_number] => 11888162 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/888162
Automatic pin placement for integrated circuits to aid circuit board design Jul 30, 2007 Issued
Array ( [id] => 175702 [patent_doc_number] => 07661085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-09 [patent_title] => 'Method and system for performing global routing on an integrated circuit design' [patent_app_type] => utility [patent_app_number] => 11/781692 [patent_app_country] => US [patent_app_date] => 2007-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 3640 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/661/07661085.pdf [firstpage_image] =>[orig_patent_app_number] => 11781692 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/781692
Method and system for performing global routing on an integrated circuit design Jul 22, 2007 Issued
Array ( [id] => 127057 [patent_doc_number] => 07712067 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-05-04 [patent_title] => 'Method and apparatus for facilitating effective and efficient optimization of short-path timing constraints' [patent_app_type] => utility [patent_app_number] => 11/879912 [patent_app_country] => US [patent_app_date] => 2007-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 11815 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/712/07712067.pdf [firstpage_image] =>[orig_patent_app_number] => 11879912 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/879912
Method and apparatus for facilitating effective and efficient optimization of short-path timing constraints Jul 18, 2007 Issued
Array ( [id] => 245217 [patent_doc_number] => 07590961 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'Integrated circuit with signal skew adjusting cell selected from cell library' [patent_app_type] => utility [patent_app_number] => 11/774022 [patent_app_country] => US [patent_app_date] => 2007-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3167 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/590/07590961.pdf [firstpage_image] =>[orig_patent_app_number] => 11774022 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/774022
Integrated circuit with signal skew adjusting cell selected from cell library Jul 5, 2007 Issued
Array ( [id] => 198611 [patent_doc_number] => 07636909 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-12-22 [patent_title] => 'Automatically generating multithreaded datapaths' [patent_app_type] => utility [patent_app_number] => 11/825372 [patent_app_country] => US [patent_app_date] => 2007-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4811 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/636/07636909.pdf [firstpage_image] =>[orig_patent_app_number] => 11825372 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/825372
Automatically generating multithreaded datapaths Jul 4, 2007 Issued
Array ( [id] => 163572 [patent_doc_number] => 07676778 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-09 [patent_title] => 'Circuit design optimization of integrated circuit based clock gated memory elements' [patent_app_type] => utility [patent_app_number] => 11/773412 [patent_app_country] => US [patent_app_date] => 2007-07-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 5050 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/676/07676778.pdf [firstpage_image] =>[orig_patent_app_number] => 11773412 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/773412
Circuit design optimization of integrated circuit based clock gated memory elements Jul 3, 2007 Issued
Array ( [id] => 158042 [patent_doc_number] => 07685547 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-03-23 [patent_title] => 'Method, system, and computer program product for generating automated assumption for compositional verification' [patent_app_type] => utility [patent_app_number] => 11/772792 [patent_app_country] => US [patent_app_date] => 2007-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8393 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/685/07685547.pdf [firstpage_image] =>[orig_patent_app_number] => 11772792 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/772792
Method, system, and computer program product for generating automated assumption for compositional verification Jul 1, 2007 Issued
Array ( [id] => 180135 [patent_doc_number] => 07657851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-02 [patent_title] => 'Device, system, and method for correction of integrated circuit design' [patent_app_type] => utility [patent_app_number] => 11/771152 [patent_app_country] => US [patent_app_date] => 2007-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6712 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/657/07657851.pdf [firstpage_image] =>[orig_patent_app_number] => 11771152 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/771152
Device, system, and method for correction of integrated circuit design Jun 28, 2007 Issued
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