
John C. Hong
Examiner (ID: 1779, Phone: (571)272-4529 , Office: P/3726 )
| Most Active Art Unit | 3726 |
| Art Unit(s) | 3726 |
| Total Applications | 2343 |
| Issued Applications | 1904 |
| Pending Applications | 53 |
| Abandoned Applications | 396 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4911485
[patent_doc_number] => 20080022252
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-24
[patent_title] => 'Method of designing semiconductor integrated circuit, designing apparatus, semiconductor integrated circuit system, semiconductor integrated circuit mounting substrate, package and semiconductor integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 11/819573
[patent_app_country] => US
[patent_app_date] => 2007-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 48
[patent_figures_cnt] => 48
[patent_no_of_words] => 20956
[patent_no_of_claims] => 77
[patent_no_of_ind_claims] => 17
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0022/20080022252.pdf
[firstpage_image] =>[orig_patent_app_number] => 11819573
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/819573 | Method of designing semiconductor integrated circuit, designing apparatus, semiconductor integrated circuit system, semiconductor integrated circuit mounting substrate, package and semiconductor integrated circuit | Jun 27, 2007 | Issued |
Array
(
[id] => 108158
[patent_doc_number] => 07725858
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-05-25
[patent_title] => 'Providing a moat capacitance'
[patent_app_type] => utility
[patent_app_number] => 11/823222
[patent_app_country] => US
[patent_app_date] => 2007-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1749
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/725/07725858.pdf
[firstpage_image] =>[orig_patent_app_number] => 11823222
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/823222 | Providing a moat capacitance | Jun 26, 2007 | Issued |
Array
(
[id] => 4854686
[patent_doc_number] => 20080320430
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-12-25
[patent_title] => 'Spare Gate Array Cell Distribution Analysis'
[patent_app_type] => utility
[patent_app_number] => 11/767542
[patent_app_country] => US
[patent_app_date] => 2007-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1315
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0320/20080320430.pdf
[firstpage_image] =>[orig_patent_app_number] => 11767542
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/767542 | Spare gate array cell distribution analysis | Jun 24, 2007 | Issued |
Array
(
[id] => 171993
[patent_doc_number] => 07669161
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-02-23
[patent_title] => 'Minimizing effects of interconnect variations in integrated circuit designs'
[patent_app_type] => utility
[patent_app_number] => 11/767292
[patent_app_country] => US
[patent_app_date] => 2007-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 11696
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 40
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/669/07669161.pdf
[firstpage_image] =>[orig_patent_app_number] => 11767292
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/767292 | Minimizing effects of interconnect variations in integrated circuit designs | Jun 21, 2007 | Issued |
Array
(
[id] => 4761355
[patent_doc_number] => 20080313581
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-12-18
[patent_title] => 'INDEPENDENT MIGRATION OF HIERARCHICAL DESIGNS WITH METHODS OF FINDING AND FIXING OPENS DURING MIGRATION'
[patent_app_type] => utility
[patent_app_number] => 11/762832
[patent_app_country] => US
[patent_app_date] => 2007-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3107
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0313/20080313581.pdf
[firstpage_image] =>[orig_patent_app_number] => 11762832
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/762832 | Independent migration of hierarchical designs with methods of finding and fixing opens during migration | Jun 13, 2007 | Issued |
Array
(
[id] => 198610
[patent_doc_number] => 07636908
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2009-12-22
[patent_title] => 'Generation of a specification of a network packet processor'
[patent_app_type] => utility
[patent_app_number] => 11/818792
[patent_app_country] => US
[patent_app_date] => 2007-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 7175
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/636/07636908.pdf
[firstpage_image] =>[orig_patent_app_number] => 11818792
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/818792 | Generation of a specification of a network packet processor | Jun 13, 2007 | Issued |
Array
(
[id] => 171998
[patent_doc_number] => 07669166
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-02-23
[patent_title] => 'Generation of a specification of a processor of network packets'
[patent_app_type] => utility
[patent_app_number] => 11/818722
[patent_app_country] => US
[patent_app_date] => 2007-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 7184
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/669/07669166.pdf
[firstpage_image] =>[orig_patent_app_number] => 11818722
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/818722 | Generation of a specification of a processor of network packets | Jun 13, 2007 | Issued |
Array
(
[id] => 5249039
[patent_doc_number] => 20070245273
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-18
[patent_title] => 'TASK CONCURRENCY MANAGEMENT DESIGN METHOD'
[patent_app_type] => utility
[patent_app_number] => 11/761275
[patent_app_country] => US
[patent_app_date] => 2007-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 35
[patent_figures_cnt] => 35
[patent_no_of_words] => 19330
[patent_no_of_claims] => 55
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0245/20070245273.pdf
[firstpage_image] =>[orig_patent_app_number] => 11761275
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/761275 | Task concurrency management design method | Jun 10, 2007 | Issued |
Array
(
[id] => 298039
[patent_doc_number] => 07543263
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-06-02
[patent_title] => 'Automatic trace shaping method'
[patent_app_type] => utility
[patent_app_number] => 11/760975
[patent_app_country] => US
[patent_app_date] => 2007-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 23
[patent_no_of_words] => 9313
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/543/07543263.pdf
[firstpage_image] =>[orig_patent_app_number] => 11760975
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/760975 | Automatic trace shaping method | Jun 10, 2007 | Issued |
Array
(
[id] => 302274
[patent_doc_number] => 07539968
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-05-26
[patent_title] => 'Iterative synthesis of an integrated circuit design for attaining power closure while maintaining existing design constraints'
[patent_app_type] => utility
[patent_app_number] => 11/759332
[patent_app_country] => US
[patent_app_date] => 2007-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2769
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 222
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/539/07539968.pdf
[firstpage_image] =>[orig_patent_app_number] => 11759332
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/759332 | Iterative synthesis of an integrated circuit design for attaining power closure while maintaining existing design constraints | Jun 6, 2007 | Issued |
Array
(
[id] => 284231
[patent_doc_number] => 07555734
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2009-06-30
[patent_title] => 'Processing constraints in computer-aided design for integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 11/810442
[patent_app_country] => US
[patent_app_date] => 2007-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 7068
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/555/07555734.pdf
[firstpage_image] =>[orig_patent_app_number] => 11810442
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/810442 | Processing constraints in computer-aided design for integrated circuits | Jun 4, 2007 | Issued |
Array
(
[id] => 4713082
[patent_doc_number] => 20080301608
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-12-04
[patent_title] => 'Methods and apparatuses for designing multiplexers'
[patent_app_type] => utility
[patent_app_number] => 11/809613
[patent_app_country] => US
[patent_app_date] => 2007-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4723
[patent_no_of_claims] => 41
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0301/20080301608.pdf
[firstpage_image] =>[orig_patent_app_number] => 11809613
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/809613 | Methods and apparatuses for designing multiplexers | May 30, 2007 | Issued |
Array
(
[id] => 118483
[patent_doc_number] => 07716618
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-05-11
[patent_title] => 'Method and system for designing semiconductor circuit devices to reduce static power consumption'
[patent_app_type] => utility
[patent_app_number] => 11/809783
[patent_app_country] => US
[patent_app_date] => 2007-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 5577
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/716/07716618.pdf
[firstpage_image] =>[orig_patent_app_number] => 11809783
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/809783 | Method and system for designing semiconductor circuit devices to reduce static power consumption | May 30, 2007 | Issued |
Array
(
[id] => 147002
[patent_doc_number] => 07694253
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-04-06
[patent_title] => 'Automatically generating an input sequence for a circuit design using mutant-based verification'
[patent_app_type] => utility
[patent_app_number] => 11/805902
[patent_app_country] => US
[patent_app_date] => 2007-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 43
[patent_no_of_words] => 23909
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 292
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/694/07694253.pdf
[firstpage_image] =>[orig_patent_app_number] => 11805902
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/805902 | Automatically generating an input sequence for a circuit design using mutant-based verification | May 23, 2007 | Issued |
Array
(
[id] => 6376167
[patent_doc_number] => 20100301487
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-12-02
[patent_title] => 'IMPROVEMENTS IN OR RELATING TO INTEGRATED CIRCUIT RELIABILITY'
[patent_app_type] => utility
[patent_app_number] => 12/599152
[patent_app_country] => US
[patent_app_date] => 2007-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3140
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0301/20100301487.pdf
[firstpage_image] =>[orig_patent_app_number] => 12599152
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/599152 | Integrated circuit reliability | May 14, 2007 | Issued |
Array
(
[id] => 47985
[patent_doc_number] => 07784014
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-08-24
[patent_title] => 'Generation of a specification of a network packet processor'
[patent_app_type] => utility
[patent_app_number] => 11/799897
[patent_app_country] => US
[patent_app_date] => 2007-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6817
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 250
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/784/07784014.pdf
[firstpage_image] =>[orig_patent_app_number] => 11799897
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/799897 | Generation of a specification of a network packet processor | May 2, 2007 | Issued |
Array
(
[id] => 7595661
[patent_doc_number] => 07620921
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-11-17
[patent_title] => 'IC chip at-functional-speed testing with process coverage evaluation'
[patent_app_type] => utility
[patent_app_number] => 11/741164
[patent_app_country] => US
[patent_app_date] => 2007-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 5811
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/620/07620921.pdf
[firstpage_image] =>[orig_patent_app_number] => 11741164
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/741164 | IC chip at-functional-speed testing with process coverage evaluation | Apr 26, 2007 | Issued |
Array
(
[id] => 4862647
[patent_doc_number] => 20080270960
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-30
[patent_title] => 'METHOD FOR INCORPORATING MILLER CAPACITANCE EFFECTS IN DIGITAL CIRCUITS FOR AN ACCURATE TIMING ANALYSIS'
[patent_app_type] => utility
[patent_app_number] => 11/741042
[patent_app_country] => US
[patent_app_date] => 2007-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 8075
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0270/20080270960.pdf
[firstpage_image] =>[orig_patent_app_number] => 11741042
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/741042 | Method for incorporating Miller capacitance effects in digital circuits for an accurate timing analysis | Apr 26, 2007 | Issued |
Array
(
[id] => 5226771
[patent_doc_number] => 20070256038
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-11-01
[patent_title] => 'SYSTEMS AND METHODS FOR PERFORMING AUTOMATED CONVERSION OF REPRESENTATIONS OF SYNCHRONOUS CIRCUIT DESIGNS TO AND FROM REPRESENTATIONS OF ASYNCHRONOUS CIRCUIT DESIGNS'
[patent_app_type] => utility
[patent_app_number] => 11/740184
[patent_app_country] => US
[patent_app_date] => 2007-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5935
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0256/20070256038.pdf
[firstpage_image] =>[orig_patent_app_number] => 11740184
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/740184 | Systems and methods for performing automated conversion of representations of synchronous circuit designs to and from representations of asynchronous circuit designs | Apr 24, 2007 | Issued |
Array
(
[id] => 261951
[patent_doc_number] => 07574685
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2009-08-11
[patent_title] => 'Method, system, and article of manufacture for reducing via failures in an integrated circuit design'
[patent_app_type] => utility
[patent_app_number] => 11/739622
[patent_app_country] => US
[patent_app_date] => 2007-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 4791
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/574/07574685.pdf
[firstpage_image] =>[orig_patent_app_number] => 11739622
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/739622 | Method, system, and article of manufacture for reducing via failures in an integrated circuit design | Apr 23, 2007 | Issued |