Search

John C. Hong

Examiner (ID: 1779, Phone: (571)272-4529 , Office: P/3726 )

Most Active Art Unit
3726
Art Unit(s)
3726
Total Applications
2343
Issued Applications
1904
Pending Applications
53
Abandoned Applications
396

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18182515 [patent_doc_number] => 20230043245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => HIGH VOLTAGE GUARD RING SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME [patent_app_type] => utility [patent_app_number] => 17/581810 [patent_app_country] => US [patent_app_date] => 2022-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21099 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17581810 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/581810
High voltage guard ring semiconductor device and method of forming same Jan 20, 2022 Issued
Array ( [id] => 18513602 [patent_doc_number] => 20230229837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => AUTO GENERATION OF DEBUG TRACE IN PRE-SILICON VERIFICATION [patent_app_type] => utility [patent_app_number] => 17/578741 [patent_app_country] => US [patent_app_date] => 2022-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9887 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17578741 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/578741
Auto generation of debug trace in pre-silicon verification Jan 18, 2022 Issued
Array ( [id] => 18720399 [patent_doc_number] => 11797745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Semiconductor device with reduced power and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/578069 [patent_app_country] => US [patent_app_date] => 2022-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 23464 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17578069 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/578069
Semiconductor device with reduced power and method of manufacturing the same Jan 17, 2022 Issued
Array ( [id] => 19740144 [patent_doc_number] => 12216979 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Method for correcting mask pattern, apparatus for correcting mask pattern and method for manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 17/647730 [patent_app_country] => US [patent_app_date] => 2022-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6591 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17647730 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/647730
Method for correcting mask pattern, apparatus for correcting mask pattern and method for manufacturing semiconductor device Jan 10, 2022 Issued
Array ( [id] => 19885954 [patent_doc_number] => 12271671 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Generation framework for ultra-low power CGRAS [patent_app_type] => utility [patent_app_number] => 17/572925 [patent_app_country] => US [patent_app_date] => 2022-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5136 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17572925 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/572925
Generation framework for ultra-low power CGRAS Jan 10, 2022 Issued
Array ( [id] => 18487215 [patent_doc_number] => 20230214561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => COMPUTER-IMPLEMENTED CIRCUIT SCHEMATIC DESIGN [patent_app_type] => utility [patent_app_number] => 17/570294 [patent_app_country] => US [patent_app_date] => 2022-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8420 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17570294 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/570294
Computer-implemented circuit schematic design Jan 5, 2022 Issued
Array ( [id] => 17736949 [patent_doc_number] => 20220222408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => SYSTEM ON CHIP ARCHITECTURE, INTERPOSER, FPGA AND METHOD OF DESIGN [patent_app_type] => utility [patent_app_number] => 17/570103 [patent_app_country] => US [patent_app_date] => 2022-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4142 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17570103 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/570103
SYSTEM ON CHIP ARCHITECTURE, INTERPOSER, FPGA AND METHOD OF DESIGN Jan 5, 2022 Abandoned
Array ( [id] => 18487217 [patent_doc_number] => 20230214563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => DYNAMIC ABSTRACT GENERATION AND SYNTHESIS FLOW WITH AREA PREDICTION [patent_app_type] => utility [patent_app_number] => 17/567328 [patent_app_country] => US [patent_app_date] => 2022-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7011 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17567328 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/567328
Dynamic abstract generation and synthesis flow with area prediction Jan 2, 2022 Issued
Array ( [id] => 18577957 [patent_doc_number] => 11734490 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Method for determining curvilinear patterns for patterning device [patent_app_type] => utility [patent_app_number] => 17/564837 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 13888 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17564837 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/564837
Method for determining curvilinear patterns for patterning device Dec 28, 2021 Issued
Array ( [id] => 18192596 [patent_doc_number] => 20230046115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => METHOD AND SYSTEM FOR CORRECTING LITHOGRAPHY PROCESS HOTSPOTS BASED ON STRESS DAMPING ADJUSTMENT [patent_app_type] => utility [patent_app_number] => 17/564241 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3932 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17564241 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/564241
Method and system for correcting lithography process hotspots based on stress damping adjustment Dec 28, 2021 Issued
Array ( [id] => 18471826 [patent_doc_number] => 20230206112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => MACHINE LEARNING FOR COMPUTATIONAL PATTERNING [patent_app_type] => utility [patent_app_number] => 17/563575 [patent_app_country] => US [patent_app_date] => 2021-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5176 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17563575 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/563575
Machine learning for computational patterning Dec 27, 2021 Issued
Array ( [id] => 19167566 [patent_doc_number] => 11983474 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-05-14 [patent_title] => Connecting random variables to coverage targets using an ensemble of static analysis, dynamic analysis and machine learning and guided constraint solving of the random variables during simulation of an integrated circuit [patent_app_type] => utility [patent_app_number] => 17/561371 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 16753 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17561371 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/561371
Connecting random variables to coverage targets using an ensemble of static analysis, dynamic analysis and machine learning and guided constraint solving of the random variables during simulation of an integrated circuit Dec 22, 2021 Issued
Array ( [id] => 19045648 [patent_doc_number] => 11934760 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-03-19 [patent_title] => Voltage impacts on delays for timing simulation [patent_app_type] => utility [patent_app_number] => 17/645882 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5536 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17645882 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/645882
Voltage impacts on delays for timing simulation Dec 22, 2021 Issued
Array ( [id] => 20117702 [patent_doc_number] => 12367411 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Enablement of sampling-optimization for gate-level simulation [patent_app_type] => utility [patent_app_number] => 17/550436 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7140 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17550436 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/550436
Enablement of sampling-optimization for gate-level simulation Dec 13, 2021 Issued
Array ( [id] => 18370952 [patent_doc_number] => 11651130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-16 [patent_title] => Method, device, and storage medium for simulating a design [patent_app_type] => utility [patent_app_number] => 17/548110 [patent_app_country] => US [patent_app_date] => 2021-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5522 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17548110 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/548110
Method, device, and storage medium for simulating a design Dec 9, 2021 Issued
Array ( [id] => 18880936 [patent_doc_number] => 20240004305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => METHOD FOR DETERMINING MASK PATTERN AND TRAINING MACHINE LEARNING MODEL [patent_app_type] => utility [patent_app_number] => 18/039697 [patent_app_country] => US [patent_app_date] => 2021-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26156 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18039697 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/039697
METHOD FOR DETERMINING MASK PATTERN AND TRAINING MACHINE LEARNING MODEL Dec 1, 2021 Pending
Array ( [id] => 18407900 [patent_doc_number] => 20230169253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => USE OF ADAPTIVE REPLACEMENT MAPS IN DIGITAL LITHOGRAPHY FOR LOCAL CELL REPLACEMENT [patent_app_type] => utility [patent_app_number] => 17/457195 [patent_app_country] => US [patent_app_date] => 2021-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5996 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17457195 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/457195
Use of adaptive replacement maps in digital lithography for local cell replacement Nov 30, 2021 Issued
Array ( [id] => 18819875 [patent_doc_number] => 20230394215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => CHIP AND PINOUT DESIGN METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 18/270215 [patent_app_country] => US [patent_app_date] => 2021-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7280 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 632 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18270215 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/270215
Chip and pinout design method therefor Nov 29, 2021 Issued
Array ( [id] => 19427101 [patent_doc_number] => 12086523 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Adaptive row patterns for custom-tiled placement fabrics for mixed height cell libraries [patent_app_type] => utility [patent_app_number] => 17/456847 [patent_app_country] => US [patent_app_date] => 2021-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 26 [patent_no_of_words] => 7872 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17456847 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/456847
Adaptive row patterns for custom-tiled placement fabrics for mixed height cell libraries Nov 28, 2021 Issued
Array ( [id] => 18856085 [patent_doc_number] => 11853669 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Relocatable FPGA modules [patent_app_type] => utility [patent_app_number] => 17/532599 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13268 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532599 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/532599
Relocatable FPGA modules Nov 21, 2021 Issued
Menu