
John C. Ingham
Examiner (ID: 10906, Phone: (571)272-8793 , Office: P/2819 )
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2819, 2897, 2814 |
| Total Applications | 619 |
| Issued Applications | 473 |
| Pending Applications | 3 |
| Abandoned Applications | 146 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8499751
[patent_doc_number] => 20120299159
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-11-29
[patent_title] => 'STRUCTURE DESIGNS AND METHODS FOR INTEGRATED CIRCUIT ALIGNMENT'
[patent_app_type] => utility
[patent_app_number] => 13/117549
[patent_app_country] => US
[patent_app_date] => 2011-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 6498
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13117549
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/117549 | Structure designs and methods for integrated circuit alignment | May 26, 2011 | Issued |
Array
(
[id] => 10022390
[patent_doc_number] => 09064884
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-06-23
[patent_title] => 'Semiconductor device having aligned side surfaces'
[patent_app_type] => utility
[patent_app_number] => 13/117592
[patent_app_country] => US
[patent_app_date] => 2011-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 27
[patent_no_of_words] => 19143
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 215
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13117592
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/117592 | Semiconductor device having aligned side surfaces | May 26, 2011 | Issued |
Array
(
[id] => 7577360
[patent_doc_number] => 20110291242
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-12-01
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/117498
[patent_app_country] => US
[patent_app_date] => 2011-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 6749
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0291/20110291242.pdf
[firstpage_image] =>[orig_patent_app_number] => 13117498
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/117498 | Semiconductor device and method of manufacturing the same | May 26, 2011 | Issued |
Array
(
[id] => 7648659
[patent_doc_number] => 20110297928
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-12-08
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/117588
[patent_app_country] => US
[patent_app_date] => 2011-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 21412
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0297/20110297928.pdf
[firstpage_image] =>[orig_patent_app_number] => 13117588
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/117588 | Storage device comprising semiconductor elements | May 26, 2011 | Issued |
Array
(
[id] => 9552792
[patent_doc_number] => 08759844
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-06-24
[patent_title] => 'Semiconductor device having elevated source and drain'
[patent_app_type] => utility
[patent_app_number] => 13/117864
[patent_app_country] => US
[patent_app_date] => 2011-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 19
[patent_no_of_words] => 5875
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13117864
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/117864 | Semiconductor device having elevated source and drain | May 26, 2011 | Issued |
Array
(
[id] => 8725990
[patent_doc_number] => 08405110
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-03-26
[patent_title] => 'Light emitting device package including a current regulator and different inclination angles'
[patent_app_type] => utility
[patent_app_number] => 13/109368
[patent_app_country] => US
[patent_app_date] => 2011-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 17
[patent_no_of_words] => 7345
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13109368
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/109368 | Light emitting device package including a current regulator and different inclination angles | May 16, 2011 | Issued |
Array
(
[id] => 6063418
[patent_doc_number] => 20110201189
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-08-18
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/094229
[patent_app_country] => US
[patent_app_date] => 2011-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5552
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0201/20110201189.pdf
[firstpage_image] =>[orig_patent_app_number] => 13094229
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/094229 | Semiconductor memory device and method of forming the same | Apr 25, 2011 | Issued |
Array
(
[id] => 8603840
[patent_doc_number] => 20130009152
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-01-10
[patent_title] => 'LIGHT-EMITTING DEVICE WITH HETEROPHASE BOUNDARIES'
[patent_app_type] => utility
[patent_app_number] => 13/635136
[patent_app_country] => US
[patent_app_date] => 2011-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3703
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13635136
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/635136 | Light-emitting device with heterophase boundaries | Mar 14, 2011 | Issued |
Array
(
[id] => 8649188
[patent_doc_number] => 20130034918
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-02-07
[patent_title] => 'MONITORING APPARATUS AND METHOD FOR IN-SITU MEASUREMENT OF WAFER THICKNESSES FOR MONITORING THE THINNING OF SEMICONDUCTOR WAFERS AND THINNING APPARATUS COMPRISING A WET ETCHING APPARATUS AND A MONITORING APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 13/521736
[patent_app_country] => US
[patent_app_date] => 2011-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 6723
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13521736
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/521736 | Monitoring apparatus and method for in-situ measurement of wafer thicknesses for monitoring the thinning of semiconductor wafers and thinning apparatus comprising a wet etching apparatus and a monitoring apparatus | Jan 9, 2011 | Issued |
Array
(
[id] => 5980089
[patent_doc_number] => 20110095346
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-04-28
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME'
[patent_app_type] => utility
[patent_app_number] => 12/984757
[patent_app_country] => US
[patent_app_date] => 2011-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4290
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0095/20110095346.pdf
[firstpage_image] =>[orig_patent_app_number] => 12984757
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/984757 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME | Jan 4, 2011 | Abandoned |
Array
(
[id] => 6075243
[patent_doc_number] => 20110140200
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-06-16
[patent_title] => 'Lateral Power MOSFET With Integrated Schottky Diode'
[patent_app_type] => utility
[patent_app_number] => 12/978476
[patent_app_country] => US
[patent_app_date] => 2010-12-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 29
[patent_no_of_words] => 9783
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0140/20110140200.pdf
[firstpage_image] =>[orig_patent_app_number] => 12978476
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/978476 | Lateral Power MOSFET With Integrated Schottky Diode | Dec 23, 2010 | Abandoned |
Array
(
[id] => 6075243
[patent_doc_number] => 20110140200
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-06-16
[patent_title] => 'Lateral Power MOSFET With Integrated Schottky Diode'
[patent_app_type] => utility
[patent_app_number] => 12/978476
[patent_app_country] => US
[patent_app_date] => 2010-12-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 29
[patent_no_of_words] => 9783
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0140/20110140200.pdf
[firstpage_image] =>[orig_patent_app_number] => 12978476
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/978476 | Lateral Power MOSFET With Integrated Schottky Diode | Dec 23, 2010 | Abandoned |
Array
(
[id] => 8205056
[patent_doc_number] => 20120126281
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-05-24
[patent_title] => 'SYSTEM FOR FLASH-FREE OVERMOLDING OF LED ARRAY SUBSTRATES'
[patent_app_type] => utility
[patent_app_number] => 12/977596
[patent_app_country] => US
[patent_app_date] => 2010-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6088
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0126/20120126281.pdf
[firstpage_image] =>[orig_patent_app_number] => 12977596
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/977596 | System for flash-free overmolding of led array substrates | Dec 22, 2010 | Issued |
Array
(
[id] => 9626430
[patent_doc_number] => 08796109
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-08-05
[patent_title] => 'Techniques for bonding substrates using an intermediate layer'
[patent_app_type] => utility
[patent_app_number] => 12/977890
[patent_app_country] => US
[patent_app_date] => 2010-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 27
[patent_no_of_words] => 12963
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12977890
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/977890 | Techniques for bonding substrates using an intermediate layer | Dec 22, 2010 | Issued |
Array
(
[id] => 8772309
[patent_doc_number] => 08426265
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-04-23
[patent_title] => 'Method for growing strain-inducing materials in CMOS circuits in a gate first flow'
[patent_app_type] => utility
[patent_app_number] => 12/938457
[patent_app_country] => US
[patent_app_date] => 2010-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 33
[patent_no_of_words] => 8889
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 322
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12938457
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/938457 | Method for growing strain-inducing materials in CMOS circuits in a gate first flow | Nov 2, 2010 | Issued |
Array
(
[id] => 7570959
[patent_doc_number] => 20110266615
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-11-03
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/938767
[patent_app_country] => US
[patent_app_date] => 2010-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 8373
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0266/20110266615.pdf
[firstpage_image] =>[orig_patent_app_number] => 12938767
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/938767 | Semiconductor device including a pillar MOS transistor | Nov 2, 2010 | Issued |
Array
(
[id] => 9027035
[patent_doc_number] => 08536618
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-09-17
[patent_title] => 'Light emitting diode structure utilizing zinc oxide nanorod arrays on one or more surfaces, and a low cost method of producing such zinc oxide nanorod arrays'
[patent_app_type] => utility
[patent_app_number] => 12/938872
[patent_app_country] => US
[patent_app_date] => 2010-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 6852
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12938872
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/938872 | Light emitting diode structure utilizing zinc oxide nanorod arrays on one or more surfaces, and a low cost method of producing such zinc oxide nanorod arrays | Nov 2, 2010 | Issued |
Array
(
[id] => 6154906
[patent_doc_number] => 20110156679
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-06-30
[patent_title] => 'INTEGRATED TRENCH GUARDED SCHOTTKY DIODE COMPATIBLE WITH POWERDIE, STRUCTURE AND METHOD'
[patent_app_type] => utility
[patent_app_number] => 12/938589
[patent_app_country] => US
[patent_app_date] => 2010-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 6630
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0156/20110156679.pdf
[firstpage_image] =>[orig_patent_app_number] => 12938589
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/938589 | Integrated trench guarded schottky diode compatible with powerdie, structure and method | Nov 2, 2010 | Issued |
Array
(
[id] => 6052991
[patent_doc_number] => 20110109351
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-05-12
[patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 12/938533
[patent_app_country] => US
[patent_app_date] => 2010-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 28
[patent_no_of_words] => 37488
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0109/20110109351.pdf
[firstpage_image] =>[orig_patent_app_number] => 12938533
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/938533 | Semiconductor device having an oxide semiconductor with a crystalline region and manufacturing method thereof | Nov 2, 2010 | Issued |
Array
(
[id] => 8166058
[patent_doc_number] => 20120104402
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-05-03
[patent_title] => 'ARCHITECTURE OF ANALOG BUFFER CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 12/938867
[patent_app_country] => US
[patent_app_date] => 2010-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4840
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0104/20120104402.pdf
[firstpage_image] =>[orig_patent_app_number] => 12938867
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/938867 | ARCHITECTURE OF ANALOG BUFFER CIRCUIT | Nov 2, 2010 | Abandoned |