John C. Loomis

Array ( [id] => 2946638 [patent_doc_number] => 05197133 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-23 [patent_title] => 'Control store addressing from multiple sources' [patent_app_type] => 1 [patent_app_number] => 7/286578 [patent_app_country] => US [patent_app_date] => 1988-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 4 [patent_no_of_words] => 7674 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 388 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/197/05197133.pdf [firstpage_image] =>[orig_patent_app_number] => 286578 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2835626 [patent_doc_number] => 05117350 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-26 [patent_title] => 'Memory address mechanism in a distributed memory architecture' [patent_app_type] => 1 [patent_app_number] => 7/284529 [patent_app_country] => US [patent_app_date] => 1988-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 25 [patent_no_of_words] => 10570 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/117/05117350.pdf [firstpage_image] =>[orig_patent_app_number] => 284529 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2804192 [patent_doc_number] => 05136717 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-04 [patent_title] => 'Realtime systolic, multiple-instruction, single-data parallel computer system' [patent_app_type] => 1 [patent_app_number] => 7/276413 [patent_app_country] => US [patent_app_date] => 1988-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 13590 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/136/05136717.pdf [firstpage_image] =>[orig_patent_app_number] => 276413 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2715758 [patent_doc_number] => 05014186 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-05-07 [patent_title] => 'Data-processing system having a packet transfer type input/output system' [patent_app_type] => 1 [patent_app_number] => 7/250996 [patent_app_country] => US [patent_app_date] => 1988-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8563 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/014/05014186.pdf [firstpage_image] =>[orig_patent_app_number] => 250996 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2640681 [patent_doc_number] => 04977537 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-12-11 [patent_title] => 'Dram nonvolatizer' [patent_app_type] => 1 [patent_app_number] => 7/248865 [patent_app_country] => US [patent_app_date] => 1988-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6846 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/977/04977537.pdf [firstpage_image] =>[orig_patent_app_number] => 248865 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2849848 [patent_doc_number] => 05121480 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-09 [patent_title] => 'Data recording system buffer management and multiple host interface control' [patent_app_type] => 1 [patent_app_number] => 7/220531 [patent_app_country] => US [patent_app_date] => 1988-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8436 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/121/05121480.pdf [firstpage_image] =>[orig_patent_app_number] => 220531 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2797832 [patent_doc_number] => 05101374 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-31 [patent_title] => 'Secure, fast storage and retrieval without interactive checking' [patent_app_type] => 1 [patent_app_number] => 7/196402 [patent_app_country] => US [patent_app_date] => 1988-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4637 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/101/05101374.pdf [firstpage_image] =>[orig_patent_app_number] => 196402 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2597743 [patent_doc_number] => 04970643 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-11-13 [patent_title] => 'Mechanism for lock-up free cache operation with a remote address translation unit' [patent_app_type] => 1 [patent_app_number] => 7/192258 [patent_app_country] => US [patent_app_date] => 1988-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 9671 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/970/04970643.pdf [firstpage_image] =>[orig_patent_app_number] => 192258 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2754809 [patent_doc_number] => 05012403 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-04-30 [patent_title] => 'Apparatus and method for replaying decoded instructions' [patent_app_type] => 1 [patent_app_number] => 7/176613 [patent_app_country] => US [patent_app_date] => 1988-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2511 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/012/05012403.pdf [firstpage_image] =>[orig_patent_app_number] => 176613 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2742778 [patent_doc_number] => 05051896 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-24 [patent_title] => 'Apparatus and method for nullifying delayed slot instructions in a pipelined computer system' [patent_app_type] => 1 [patent_app_number] => 7/170520 [patent_app_country] => US [patent_app_date] => 1988-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3630 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/051/05051896.pdf [firstpage_image] =>[orig_patent_app_number] => 170520 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2731454 [patent_doc_number] => 05025412 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-06-18 [patent_title] => 'Universal bus interface' [patent_app_type] => 1 [patent_app_number] => 7/157294 [patent_app_country] => US [patent_app_date] => 1988-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4030 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 366 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/025/05025412.pdf [firstpage_image] =>[orig_patent_app_number] => 157294 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2725248 [patent_doc_number] => 05053990 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-01 [patent_title] => 'Program/erase selection for flash memory' [patent_app_type] => 1 [patent_app_number] => 7/157361 [patent_app_country] => US [patent_app_date] => 1988-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4531 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 311 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/053/05053990.pdf [firstpage_image] =>[orig_patent_app_number] => 157361 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2717368 [patent_doc_number] => 05056002 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-08 [patent_title] => 'Cache memory for use with multiprocessor systems' [patent_app_type] => 1 [patent_app_number] => 7/153890 [patent_app_country] => US [patent_app_date] => 1988-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2705 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 494 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/056/05056002.pdf [firstpage_image] =>[orig_patent_app_number] => 153890 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2716769 [patent_doc_number] => 05014236 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-05-07 [patent_title] => 'Input/output bus expansion interface' [patent_app_type] => 1 [patent_app_number] => 7/149796 [patent_app_country] => US [patent_app_date] => 1988-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4188 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/014/05014236.pdf [firstpage_image] =>[orig_patent_app_number] => 149796 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2756038 [patent_doc_number] => 05016165 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-05-14 [patent_title] => 'Direct memory access controlled system' [patent_app_type] => 1 [patent_app_number] => 7/142949 [patent_app_country] => US [patent_app_date] => 1988-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5635 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/016/05016165.pdf [firstpage_image] =>[orig_patent_app_number] => 142949 [rel_patent_id] =>[rel_patent_doc_number] =>)