Search

John D. Blanton

Examiner (ID: 12088)

Most Active Art Unit
2466
Art Unit(s)
2466, 2619, 2419
Total Applications
1157
Issued Applications
871
Pending Applications
78
Abandoned Applications
233

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11306637 [patent_doc_number] => 09514035 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-12-06 [patent_title] => 'Coverage driven generation of constrained random stimuli' [patent_app_type] => utility [patent_app_number] => 14/582328 [patent_app_country] => US [patent_app_date] => 2014-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3641 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14582328 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/582328
Coverage driven generation of constrained random stimuli Dec 23, 2014 Issued
Array ( [id] => 10991709 [patent_doc_number] => 20160188654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'RULE BASED DATA NORMALIZATION UTILIZING MULTI-KEY SORTING' [patent_app_type] => utility [patent_app_number] => 14/582510 [patent_app_country] => US [patent_app_date] => 2014-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12337 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14582510 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/582510
Rule based data normalization utilizing multi-key sorting Dec 23, 2014 Issued
Array ( [id] => 11333119 [patent_doc_number] => 09524365 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-12-20 [patent_title] => 'Efficient monte carlo flow via failure probability modeling' [patent_app_type] => utility [patent_app_number] => 14/581958 [patent_app_country] => US [patent_app_date] => 2014-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5000 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14581958 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/581958
Efficient monte carlo flow via failure probability modeling Dec 22, 2014 Issued
Array ( [id] => 11796046 [patent_doc_number] => 09405877 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-08-02 [patent_title] => 'System and method of fast phase aligned local generation of clocks on multiple FPGA system' [patent_app_type] => utility [patent_app_number] => 14/580014 [patent_app_country] => US [patent_app_date] => 2014-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5554 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14580014 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/580014
System and method of fast phase aligned local generation of clocks on multiple FPGA system Dec 21, 2014 Issued
Array ( [id] => 10204474 [patent_doc_number] => 20150089462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-26 [patent_title] => 'CONCURRENT OPTIMIZATION OF TIMING, AREA, AND LEAKAGE POWER' [patent_app_type] => utility [patent_app_number] => 14/557920 [patent_app_country] => US [patent_app_date] => 2014-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7076 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14557920 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/557920
Concurrent optimization of timing, area, and leakage power Dec 1, 2014 Issued
Array ( [id] => 10462627 [patent_doc_number] => 20150347643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'PHYSICAL AWARE TECHNOLOGY MAPPING IN SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 14/547324 [patent_app_country] => US [patent_app_date] => 2014-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3944 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14547324 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/547324
Physical aware technology mapping in synthesis Nov 18, 2014 Issued
Array ( [id] => 12173380 [patent_doc_number] => 09891519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-13 [patent_title] => 'Free form fracturing method for electronic or optical lithography using resist threshold control' [patent_app_type] => utility [patent_app_number] => 15/033016 [patent_app_country] => US [patent_app_date] => 2014-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 33 [patent_no_of_words] => 6470 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15033016 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/033016
Free form fracturing method for electronic or optical lithography using resist threshold control Oct 26, 2014 Issued
Array ( [id] => 9841114 [patent_doc_number] => 20150033196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-29 [patent_title] => 'Clustering For Processing Of Circuit Design Data' [patent_app_type] => utility [patent_app_number] => 14/504612 [patent_app_country] => US [patent_app_date] => 2014-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7241 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14504612 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/504612
Clustering For Processing Of Circuit Design Data Oct 1, 2014 Abandoned
Array ( [id] => 14460623 [patent_doc_number] => 10326288 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Method and device for the voltage-controlled self-deactivation of electronic components or battery cells [patent_app_type] => utility [patent_app_number] => 15/028901 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4982 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15028901 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/028901
Method and device for the voltage-controlled self-deactivation of electronic components or battery cells Sep 29, 2014 Issued
Array ( [id] => 9789772 [patent_doc_number] => 20150001716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'DE-POP ON-DEVICE DECOUPLING FOR BGA' [patent_app_type] => utility [patent_app_number] => 14/489110 [patent_app_country] => US [patent_app_date] => 2014-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1974 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14489110 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/489110
DE-POP ON-DEVICE DECOUPLING FOR BGA Sep 16, 2014 Abandoned
Array ( [id] => 11017543 [patent_doc_number] => 20160214496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-28 [patent_title] => 'CHARGING SYSTEM AND PAIRING METHOD' [patent_app_type] => utility [patent_app_number] => 14/914194 [patent_app_country] => US [patent_app_date] => 2014-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 14364 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14914194 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/914194
Charging system and pairing method Aug 12, 2014 Issued
Array ( [id] => 11763809 [patent_doc_number] => 09372226 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-21 [patent_title] => 'Wafer test structures and methods of providing wafer test structures' [patent_app_type] => utility [patent_app_number] => 14/337290 [patent_app_country] => US [patent_app_date] => 2014-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6063 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14337290 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/337290
Wafer test structures and methods of providing wafer test structures Jul 21, 2014 Issued
Array ( [id] => 10111612 [patent_doc_number] => 09147029 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-29 [patent_title] => 'Stretch dummy cell insertion in FinFET process' [patent_app_type] => utility [patent_app_number] => 14/325868 [patent_app_country] => US [patent_app_date] => 2014-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 45 [patent_no_of_words] => 6834 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14325868 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/325868
Stretch dummy cell insertion in FinFET process Jul 7, 2014 Issued
Array ( [id] => 10111613 [patent_doc_number] => 09147030 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-29 [patent_title] => 'Multiple-instantiated-module (mim) aware pin assignment' [patent_app_type] => utility [patent_app_number] => 14/326002 [patent_app_country] => US [patent_app_date] => 2014-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5772 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14326002 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/326002
Multiple-instantiated-module (mim) aware pin assignment Jul 7, 2014 Issued
Array ( [id] => 12228628 [patent_doc_number] => 09915869 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-03-13 [patent_title] => 'Single mask set used for interposer fabrication of multiple products' [patent_app_type] => utility [patent_app_number] => 14/321591 [patent_app_country] => US [patent_app_date] => 2014-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 6616 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14321591 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/321591
Single mask set used for interposer fabrication of multiple products Jun 30, 2014 Issued
Array ( [id] => 12632496 [patent_doc_number] => 20180102662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-12 [patent_title] => CANCEL VOLTAGE OFFSET OF OPERATIONAL AMPLIFIER [patent_app_type] => utility [patent_app_number] => 15/308316 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4031 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15308316 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/308316
Cancel voltage offset of operational amplifier Jun 29, 2014 Issued
Array ( [id] => 11890105 [patent_doc_number] => 09760667 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-12 [patent_title] => 'Method, system, and computer program product for implementing prototyping and floorplanning of electronic circuit designs' [patent_app_type] => utility [patent_app_number] => 14/320444 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 14647 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14320444 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/320444
Method, system, and computer program product for implementing prototyping and floorplanning of electronic circuit designs Jun 29, 2014 Issued
Array ( [id] => 11897308 [patent_doc_number] => 09767245 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-19 [patent_title] => 'Method, system, and computer program product for improving mask designs and manufacturability of electronic designs for multi-exposure lithography' [patent_app_type] => utility [patent_app_number] => 14/320594 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 11718 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14320594 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/320594
Method, system, and computer program product for improving mask designs and manufacturability of electronic designs for multi-exposure lithography Jun 29, 2014 Issued
Array ( [id] => 10111617 [patent_doc_number] => 09147034 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-09-29 [patent_title] => 'Circuit layout verification method' [patent_app_type] => utility [patent_app_number] => 14/319513 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6422 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14319513 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/319513
Circuit layout verification method Jun 29, 2014 Issued
Array ( [id] => 9795176 [patent_doc_number] => 20150007121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'CHIP CROSS-SECTION IDENTIFICATION AND RENDERING DURING FAILURE ANALYSIS' [patent_app_type] => utility [patent_app_number] => 14/318552 [patent_app_country] => US [patent_app_date] => 2014-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7851 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14318552 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/318552
Chip cross-section identification and rendering during failure analysis Jun 26, 2014 Issued
Menu