Search

John D. Blanton

Examiner (ID: 12088)

Most Active Art Unit
2466
Art Unit(s)
2466, 2619, 2419
Total Applications
1157
Issued Applications
871
Pending Applications
78
Abandoned Applications
233

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9974374 [patent_doc_number] => 09021410 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-04-28 [patent_title] => 'Electronic system with multi-cycle simulation coverage mechanism and method of operation thereof' [patent_app_type] => utility [patent_app_number] => 14/182628 [patent_app_country] => US [patent_app_date] => 2014-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7760 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14182628 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/182628
Electronic system with multi-cycle simulation coverage mechanism and method of operation thereof Feb 17, 2014 Issued
Array ( [id] => 11220535 [patent_doc_number] => 09448872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-20 [patent_title] => 'Hardware state data logger for silicon debug' [patent_app_type] => utility [patent_app_number] => 14/179191 [patent_app_country] => US [patent_app_date] => 2014-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8518 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14179191 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/179191
Hardware state data logger for silicon debug Feb 11, 2014 Issued
Array ( [id] => 10328174 [patent_doc_number] => 20150213178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'TIER BASED LAYER PROMOTION AND DEMOTION' [patent_app_type] => utility [patent_app_number] => 14/166974 [patent_app_country] => US [patent_app_date] => 2014-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6942 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14166974 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/166974
Tier based layer promotion and demotion Jan 28, 2014 Issued
Array ( [id] => 11637150 [patent_doc_number] => 09659125 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-23 [patent_title] => 'Computer implemented system and method for generating a layout of a cell defining a circuit component' [patent_app_type] => utility [patent_app_number] => 14/165623 [patent_app_country] => US [patent_app_date] => 2014-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10442 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14165623 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/165623
Computer implemented system and method for generating a layout of a cell defining a circuit component Jan 27, 2014 Issued
Array ( [id] => 10328181 [patent_doc_number] => 20150213185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'METHOD, COMPUTER SYSTEM AND COMPUTER-READABLE STORAGE MEDIUM FOR CREATING A LAYOUT OF AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/166044 [patent_app_country] => US [patent_app_date] => 2014-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 14298 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14166044 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/166044
Method, computer system and computer-readable storage medium for creating a layout of an integrated circuit Jan 27, 2014 Issued
Array ( [id] => 10328168 [patent_doc_number] => 20150213172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'METHOD FOR MEASURING AND ANALYZING SURFACE STRUCTURE OF CHIP OR WAFER' [patent_app_type] => utility [patent_app_number] => 14/165043 [patent_app_country] => US [patent_app_date] => 2014-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5022 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14165043 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/165043
Method for measuring and analyzing surface structure of chip or wafer Jan 26, 2014 Issued
Array ( [id] => 10569468 [patent_doc_number] => 09292638 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-03-22 [patent_title] => 'Method and apparatus for performing timing closure analysis when performing register retiming' [patent_app_type] => utility [patent_app_number] => 14/159858 [patent_app_country] => US [patent_app_date] => 2014-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 8407 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14159858 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/159858
Method and apparatus for performing timing closure analysis when performing register retiming Jan 20, 2014 Issued
Array ( [id] => 9980640 [patent_doc_number] => 09026971 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-05-05 [patent_title] => 'Multi-patterning conflict free integrated circuit design' [patent_app_type] => utility [patent_app_number] => 14/148898 [patent_app_country] => US [patent_app_date] => 2014-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6332 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14148898 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/148898
Multi-patterning conflict free integrated circuit design Jan 6, 2014 Issued
Array ( [id] => 10301560 [patent_doc_number] => 20150186560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'SYSTEM FOR AND METHOD OF COMBINING CMOS INVERTERS OF MULTIPLE DRIVE STRENGTHS TO CREATE TUNE-ABLE CLOCK INVERTERS OF VARIABLE DRIVE STRENGTHS IN HYBRID TREE-MESH CLOCK DISTRIBUTION NETWORKS' [patent_app_type] => utility [patent_app_number] => 14/141076 [patent_app_country] => US [patent_app_date] => 2013-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3867 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14141076 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/141076
System for and method of combining CMOS inverters of multiple drive strengths to create tune-able clock inverters of variable drive strengths in hybrid tree-mesh clock distribution networks Dec 25, 2013 Issued
Array ( [id] => 9564064 [patent_doc_number] => 20140181776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'WHAT-IF PARTITIONING AND TIMING' [patent_app_type] => utility [patent_app_number] => 14/140248 [patent_app_country] => US [patent_app_date] => 2013-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4273 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14140248 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/140248
Semiconductor integrated circuit partitioning and timing Dec 23, 2013 Issued
Array ( [id] => 9571921 [patent_doc_number] => 20140189634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'PRIORI CORNER AND MODE REDUCTION' [patent_app_type] => utility [patent_app_number] => 14/139568 [patent_app_country] => US [patent_app_date] => 2013-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4887 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14139568 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/139568
Priori corner and mode reduction Dec 22, 2013 Issued
Array ( [id] => 9637314 [patent_doc_number] => 20140215423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-31 [patent_title] => 'SEMICONDUCTOR DEVICE DESIGN METHOD AND DESIGN APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/132428 [patent_app_country] => US [patent_app_date] => 2013-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6639 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14132428 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/132428
Semiconductor device design method and design apparatus Dec 17, 2013 Issued
Array ( [id] => 10021581 [patent_doc_number] => 09064069 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-06-23 [patent_title] => 'Creating an end point report based on a comprehensive timing report' [patent_app_type] => utility [patent_app_number] => 14/132068 [patent_app_country] => US [patent_app_date] => 2013-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6302 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14132068 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/132068
Creating an end point report based on a comprehensive timing report Dec 17, 2013 Issued
Array ( [id] => 9507219 [patent_doc_number] => 08745548 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-03 [patent_title] => 'Perturbational technique for co-optimizing design rules and illumination conditions for lithography process' [patent_app_type] => utility [patent_app_number] => 14/102086 [patent_app_country] => US [patent_app_date] => 2013-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3711 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14102086 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/102086
Perturbational technique for co-optimizing design rules and illumination conditions for lithography process Dec 9, 2013 Issued
Array ( [id] => 9746614 [patent_doc_number] => 20140282333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'DESIGN SUPPORT APPARATUS AND DESIGN SUPPORT METHOD' [patent_app_type] => utility [patent_app_number] => 14/101973 [patent_app_country] => US [patent_app_date] => 2013-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 11262 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14101973 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/101973
Support apparatus and design support method Dec 9, 2013 Issued
Array ( [id] => 10218873 [patent_doc_number] => 20150103866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-16 [patent_title] => 'DIGITAL TEMPERATURE ESTIMATORS (DTEs) DISPOSED IN INTEGRATED CIRCUITS (ICs) FOR ESTIMATING TEMPERATURE WITHIN THE ICs, AND RELATED SYSTEMS AND METHODS' [patent_app_type] => utility [patent_app_number] => 14/091390 [patent_app_country] => US [patent_app_date] => 2013-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12173 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14091390 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/091390
DIGITAL TEMPERATURE ESTIMATORS (DTEs) DISPOSED IN INTEGRATED CIRCUITS (ICs) FOR ESTIMATING TEMPERATURE WITHIN THE ICs, AND RELATED SYSTEMS AND METHODS Nov 26, 2013 Abandoned
Array ( [id] => 10264974 [patent_doc_number] => 20150149971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-28 [patent_title] => 'OPTIMIZING LITHOGRAPHY MASKS FOR VLSI CHIP DESIGN' [patent_app_type] => utility [patent_app_number] => 14/091102 [patent_app_country] => US [patent_app_date] => 2013-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6811 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14091102 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/091102
Optimizing lithography masks for VLSI chip design Nov 25, 2013 Issued
Array ( [id] => 10260483 [patent_doc_number] => 20150145480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-28 [patent_title] => 'HIGH CAPACITY BATTERIES WITH ON-DEMAND FAST CHARGE CAPABILITY' [patent_app_type] => utility [patent_app_number] => 14/089885 [patent_app_country] => US [patent_app_date] => 2013-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4770 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14089885 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/089885
High capacity batteries with on-demand fast charge capability Nov 25, 2013 Issued
Array ( [id] => 9768602 [patent_doc_number] => 20140292265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-02 [patent_title] => 'Active Charge Equilibrium System for Lithium Battery Pack' [patent_app_type] => utility [patent_app_number] => 14/089037 [patent_app_country] => US [patent_app_date] => 2013-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2413 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14089037 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/089037
Active charge equilibrium system for lithium battery pack Nov 24, 2013 Issued
Array ( [id] => 9515759 [patent_doc_number] => 20140152251 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-05 [patent_title] => 'APPARATUS AND METHOD FOR CHARGE CONTROL IN WIRELESS CHARGING SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/089112 [patent_app_country] => US [patent_app_date] => 2013-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 19595 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14089112 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/089112
Apparatus and method for charge control in wireless charging system Nov 24, 2013 Issued
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