Search

John D. Blanton

Examiner (ID: 12088)

Most Active Art Unit
2466
Art Unit(s)
2466, 2619, 2419
Total Applications
1157
Issued Applications
871
Pending Applications
78
Abandoned Applications
233

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9195699 [patent_doc_number] => 20130335014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'POWER TOOL BATTERY PACK WIRELESS CHARGER' [patent_app_type] => utility [patent_app_number] => 13/769637 [patent_app_country] => US [patent_app_date] => 2013-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1936 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13769637 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/769637
Power tool battery pack wireless charger Feb 17, 2013 Issued
Array ( [id] => 9297214 [patent_doc_number] => 20140040848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-06 [patent_title] => 'Controllable Turn-Around Time For Post Tape-Out Flow' [patent_app_type] => utility [patent_app_number] => 13/767870 [patent_app_country] => US [patent_app_date] => 2013-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6705 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13767870 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/767870
Controllable Turn-Around Time For Post Tape-Out Flow Feb 13, 2013 Abandoned
Array ( [id] => 9214119 [patent_doc_number] => 20140013296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-09 [patent_title] => 'ESD ANALYSIS APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/760943 [patent_app_country] => US [patent_app_date] => 2013-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8436 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13760943 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/760943
ESD analysis apparatus Feb 5, 2013 Issued
Array ( [id] => 10111614 [patent_doc_number] => 09147031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-29 [patent_title] => 'Analysis of chip-mean variation and independent intra-die variation for chip yield determination' [patent_app_type] => utility [patent_app_number] => 13/755726 [patent_app_country] => US [patent_app_date] => 2013-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5726 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13755726 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/755726
Analysis of chip-mean variation and independent intra-die variation for chip yield determination Jan 30, 2013 Issued
Array ( [id] => 9500246 [patent_doc_number] => 08739087 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-27 [patent_title] => 'System and method for large multiplexer identification and creation in a design of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 13/756083 [patent_app_country] => US [patent_app_date] => 2013-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3412 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13756083 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/756083
System and method for large multiplexer identification and creation in a design of an integrated circuit Jan 30, 2013 Issued
Array ( [id] => 9926469 [patent_doc_number] => 08984456 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-17 [patent_title] => 'Macro timing analysis device, macro boundary path timing analysis method and macro boundary path timing analysis program' [patent_app_type] => utility [patent_app_number] => 13/753143 [patent_app_country] => US [patent_app_date] => 2013-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8235 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13753143 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/753143
Macro timing analysis device, macro boundary path timing analysis method and macro boundary path timing analysis program Jan 28, 2013 Issued
Array ( [id] => 9652371 [patent_doc_number] => 08806407 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-12 [patent_title] => 'Multiple-instantiated-module (MIM) aware pin assignment' [patent_app_type] => utility [patent_app_number] => 13/753103 [patent_app_country] => US [patent_app_date] => 2013-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5733 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13753103 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/753103
Multiple-instantiated-module (MIM) aware pin assignment Jan 28, 2013 Issued
Array ( [id] => 9012599 [patent_doc_number] => 08527920 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-09-03 [patent_title] => 'Automated synthesis of high-performance two operand binary parallel prefix adder' [patent_app_type] => utility [patent_app_number] => 13/752934 [patent_app_country] => US [patent_app_date] => 2013-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 10405 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13752934 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/752934
Automated synthesis of high-performance two operand binary parallel prefix adder Jan 28, 2013 Issued
Array ( [id] => 10847868 [patent_doc_number] => 08875069 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-10-28 [patent_title] => 'System and method for generating constrained random values associated with an electronic design' [patent_app_type] => utility [patent_app_number] => 13/749133 [patent_app_country] => US [patent_app_date] => 2013-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4861 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13749133 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/749133
System and method for generating constrained random values associated with an electronic design Jan 23, 2013 Issued
Array ( [id] => 9527690 [patent_doc_number] => 08751979 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-06-10 [patent_title] => 'Determining the gradient and Hessian of the image log slope for design rule optimization for accelerating source mask optimization (SMO)' [patent_app_type] => utility [patent_app_number] => 13/741802 [patent_app_country] => US [patent_app_date] => 2013-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 54 [patent_no_of_words] => 11510 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13741802 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/741802
Determining the gradient and Hessian of the image log slope for design rule optimization for accelerating source mask optimization (SMO) Jan 14, 2013 Issued
Array ( [id] => 8815962 [patent_doc_number] => 20130117007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-09 [patent_title] => 'METHOD AND APPARATUS FOR TURNING CUSTOM PROTOTYPE BOARDS INTO CO-SIMULATION, CO-EMULATION SYSTEMS' [patent_app_type] => utility [patent_app_number] => 13/730543 [patent_app_country] => US [patent_app_date] => 2012-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4278 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13730543 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/730543
Method and apparatus for turning custom prototype boards into co-simulation, co-emulation systems Dec 27, 2012 Issued
Array ( [id] => 9563778 [patent_doc_number] => 20140181491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'FIELD-PROGRAMMABLE MODULE FOR INTERFACE BRIDGING AND INPUT/OUTPUT EXPANSION' [patent_app_type] => utility [patent_app_number] => 13/726829 [patent_app_country] => US [patent_app_date] => 2012-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7073 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13726829 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/726829
Field-programmable module for interface bridging and input/output expansion Dec 25, 2012 Issued
Array ( [id] => 9555844 [patent_doc_number] => 08762917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-24 [patent_title] => 'Automatically modifying a circuit layout to perform electromagnetic simulation' [patent_app_type] => utility [patent_app_number] => 13/723773 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 3927 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13723773 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/723773
Automatically modifying a circuit layout to perform electromagnetic simulation Dec 20, 2012 Issued
Array ( [id] => 8794187 [patent_doc_number] => 20130111156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-02 [patent_title] => 'FLEXIBLE PIN ALLOCATION' [patent_app_type] => utility [patent_app_number] => 13/725215 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6930 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13725215 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/725215
Flexible pin allocation Dec 20, 2012 Issued
Array ( [id] => 11552103 [patent_doc_number] => 09620968 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-11 [patent_title] => 'Power reserve apparatus, power system, and electric vehicle' [patent_app_type] => utility [patent_app_number] => 14/365870 [patent_app_country] => US [patent_app_date] => 2012-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 17861 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14365870 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/365870
Power reserve apparatus, power system, and electric vehicle Dec 16, 2012 Issued
Array ( [id] => 9548887 [patent_doc_number] => 20140173535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-19 [patent_title] => 'ANALYSIS OF CHIP-MEAN VARIATION AND INDEPENDENT INTRA-DIE VARIATION FOR CHIP YIELD DETERMINATION' [patent_app_type] => utility [patent_app_number] => 13/716283 [patent_app_country] => US [patent_app_date] => 2012-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5681 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13716283 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/716283
ANALYSIS OF CHIP-MEAN VARIATION AND INDEPENDENT INTRA-DIE VARIATION FOR CHIP YIELD DETERMINATION Dec 16, 2012 Abandoned
Array ( [id] => 10930239 [patent_doc_number] => 20140333259 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-13 [patent_title] => 'ELECTRONIC UNIT AND POWER FEEDING SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/366075 [patent_app_country] => US [patent_app_date] => 2012-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9855 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14366075 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/366075
Electronic unit and power feeding system Dec 12, 2012 Issued
Array ( [id] => 9248614 [patent_doc_number] => 08612916 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-12-17 [patent_title] => 'System and method for import and export of design constraints' [patent_app_type] => utility [patent_app_number] => 13/709733 [patent_app_country] => US [patent_app_date] => 2012-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4811 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13709733 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/709733
System and method for import and export of design constraints Dec 9, 2012 Issued
Array ( [id] => 9520399 [patent_doc_number] => 20140156891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-05 [patent_title] => 'SYSTEMS AND METHODS FOR AUTOMATICALLY GENERATING MASTER-SLAVE LATCH STRUCTURES WITH FULLY REGISTERED FLOW CONTROL' [patent_app_type] => utility [patent_app_number] => 13/693869 [patent_app_country] => US [patent_app_date] => 2012-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4642 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13693869 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/693869
SYSTEMS AND METHODS FOR AUTOMATICALLY GENERATING MASTER-SLAVE LATCH STRUCTURES WITH FULLY REGISTERED FLOW CONTROL Dec 3, 2012 Abandoned
Array ( [id] => 10917068 [patent_doc_number] => 20140320087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-30 [patent_title] => 'CONTROL APPARATUS AND CONTROL METHOD FOR ELECTRICITY STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 14/361499 [patent_app_country] => US [patent_app_date] => 2012-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9695 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14361499 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/361499
CONTROL APPARATUS AND CONTROL METHOD FOR ELECTRICITY STORAGE DEVICE Nov 28, 2012 Abandoned
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