Search

John D. Blanton

Examiner (ID: 12088)

Most Active Art Unit
2466
Art Unit(s)
2466, 2619, 2419
Total Applications
1157
Issued Applications
871
Pending Applications
78
Abandoned Applications
233

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9404878 [patent_doc_number] => 08694943 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-04-08 [patent_title] => 'Methods, systems, and computer program product for implementing electronic designs with connectivity and constraint awareness' [patent_app_type] => utility [patent_app_number] => 13/445874 [patent_app_country] => US [patent_app_date] => 2012-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13569 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13445874 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/445874
Methods, systems, and computer program product for implementing electronic designs with connectivity and constraint awareness Apr 11, 2012 Issued
Array ( [id] => 8672596 [patent_doc_number] => 20130047134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-21 [patent_title] => 'VIEWING AND DEBUGGING HDL DESIGNS HAVING SYSTEMVERILOG INTERFACE CONSTRUCTS' [patent_app_type] => utility [patent_app_number] => 13/443523 [patent_app_country] => US [patent_app_date] => 2012-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4493 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13443523 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/443523
Viewing and debugging HDL designs having SystemVerilog interface constructs Apr 9, 2012 Issued
Array ( [id] => 9102874 [patent_doc_number] => 08566768 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-22 [patent_title] => 'Best clock frequency search for FPGA-based design' [patent_app_type] => utility [patent_app_number] => 13/441053 [patent_app_country] => US [patent_app_date] => 2012-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5459 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 395 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13441053 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/441053
Best clock frequency search for FPGA-based design Apr 5, 2012 Issued
13/433154 EDGE TRIGGERED CALIBRATION Mar 27, 2012 Abandoned
Array ( [id] => 8383385 [patent_doc_number] => 20120227015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-06 [patent_title] => 'PERTURBATIONAL TECHNIQUE FOR CO-OPTIMIZING DESIGN RULES AND ILLUMINATION CONDITIONS FOR LITHOGRAPHY PROCESS' [patent_app_type] => utility [patent_app_number] => 13/410088 [patent_app_country] => US [patent_app_date] => 2012-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3696 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13410088 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/410088
Perturbational technique for co-optimizing design rules and illumination conditions for lithography process Feb 29, 2012 Issued
Array ( [id] => 10100405 [patent_doc_number] => 09136727 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-15 [patent_title] => 'Battery charging control device' [patent_app_type] => utility [patent_app_number] => 13/817769 [patent_app_country] => US [patent_app_date] => 2012-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4541 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13817769 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/817769
Battery charging control device Feb 29, 2012 Issued
Array ( [id] => 8613902 [patent_doc_number] => 20130019214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-17 [patent_title] => 'THREE-DIMENSIONAL INTEGRATED CIRCUIT DESIGN DEVICE, THREE-DIMENSIONAL INTEGRATED CIRCUIT DESIGN, METHOD, AND PROGRAM' [patent_app_type] => utility [patent_app_number] => 13/637818 [patent_app_country] => US [patent_app_date] => 2012-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8882 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13637818 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/637818
Three-dimensional integrated circuit design device, three-dimensional integrated circuit design, method, and program Feb 16, 2012 Issued
Array ( [id] => 9172063 [patent_doc_number] => 20130314048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-28 [patent_title] => 'BATTERY DEVICE, BATTERY MANAGEMENT METHOD, AND ELECTRONIC APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/984302 [patent_app_country] => US [patent_app_date] => 2012-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6442 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13984302 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/984302
Battery device, battery management method, and electronic apparatus Feb 13, 2012 Issued
Array ( [id] => 8906606 [patent_doc_number] => 20130174109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-04 [patent_title] => 'DEVICE MISMATCH CORNER MODEL' [patent_app_type] => utility [patent_app_number] => 13/342374 [patent_app_country] => US [patent_app_date] => 2012-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 11231 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13342374 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/342374
Device mismatch corner model Jan 2, 2012 Issued
Array ( [id] => 10611468 [patent_doc_number] => 09331515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-03 [patent_title] => 'System for charging an energy store, and method for operating the charging system' [patent_app_type] => utility [patent_app_number] => 13/984555 [patent_app_country] => US [patent_app_date] => 2011-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2996 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13984555 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/984555
System for charging an energy store, and method for operating the charging system Dec 28, 2011 Issued
Array ( [id] => 9714557 [patent_doc_number] => 08839160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-16 [patent_title] => 'Masks for double patterning photolithography' [patent_app_type] => utility [patent_app_number] => 13/977630 [patent_app_country] => US [patent_app_date] => 2011-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5564 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13977630 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/977630
Masks for double patterning photolithography Dec 28, 2011 Issued
Array ( [id] => 8998276 [patent_doc_number] => 08522182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-27 [patent_title] => 'Generation of an end point report for a timing simulation of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 13/314514 [patent_app_country] => US [patent_app_date] => 2011-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8172 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13314514 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/314514
Generation of an end point report for a timing simulation of an integrated circuit Dec 7, 2011 Issued
Array ( [id] => 13144195 [patent_doc_number] => 10089432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-02 [patent_title] => Rule-check waiver [patent_app_type] => utility [patent_app_number] => 13/304094 [patent_app_country] => US [patent_app_date] => 2011-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 8935 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13304094 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/304094
Rule-check waiver Nov 22, 2011 Issued
Array ( [id] => 9472551 [patent_doc_number] => 08726200 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-13 [patent_title] => 'Recognition of template patterns with mask information' [patent_app_type] => utility [patent_app_number] => 13/303374 [patent_app_country] => US [patent_app_date] => 2011-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5885 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13303374 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/303374
Recognition of template patterns with mask information Nov 22, 2011 Issued
Array ( [id] => 13144195 [patent_doc_number] => 10089432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-02 [patent_title] => Rule-check waiver [patent_app_type] => utility [patent_app_number] => 13/304094 [patent_app_country] => US [patent_app_date] => 2011-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 8935 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13304094 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/304094
Rule-check waiver Nov 22, 2011 Issued
Array ( [id] => 9172057 [patent_doc_number] => 20130314042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-28 [patent_title] => 'Method for Ascertaining the Open Circuit Voltage of a Battery, Battery with a Module for Ascertaining the Open Circuit Voltage and a Motor Vehicle Having a Corresponding Battery' [patent_app_type] => utility [patent_app_number] => 13/990507 [patent_app_country] => US [patent_app_date] => 2011-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2316 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13990507 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/990507
Method for Ascertaining the Open Circuit Voltage of a Battery, Battery with a Module for Ascertaining the Open Circuit Voltage and a Motor Vehicle Having a Corresponding Battery Nov 20, 2011 Abandoned
Array ( [id] => 9326347 [patent_doc_number] => 08661384 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-25 [patent_title] => 'Verification support apparatus, verifying apparatus, computer product, verification support method, and verifying method' [patent_app_type] => utility [patent_app_number] => 13/298354 [patent_app_country] => US [patent_app_date] => 2011-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 52 [patent_no_of_words] => 18509 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13298354 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/298354
Verification support apparatus, verifying apparatus, computer product, verification support method, and verifying method Nov 16, 2011 Issued
Array ( [id] => 8985299 [patent_doc_number] => 08516429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'Circuit optimization method and apparatus for analog circuit migration' [patent_app_type] => utility [patent_app_number] => 13/640594 [patent_app_country] => US [patent_app_date] => 2011-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5578 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13640594 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/640594
Circuit optimization method and apparatus for analog circuit migration Nov 14, 2011 Issued
Array ( [id] => 8303261 [patent_doc_number] => 20120185814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-19 [patent_title] => 'INDICATOR CALCULATION METHOD AND APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/280623 [patent_app_country] => US [patent_app_date] => 2011-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7295 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13280623 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/280623
Indicator calculation method and apparatus Oct 24, 2011 Issued
Array ( [id] => 8873094 [patent_doc_number] => 08468483 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-18 [patent_title] => 'Method, system and program storage device for performing a parameterized statistical static timing analysis (SSTA) of an integrated circuit taking into account setup and hold margin interdependence' [patent_app_type] => utility [patent_app_number] => 13/279373 [patent_app_country] => US [patent_app_date] => 2011-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11985 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13279373 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/279373
Method, system and program storage device for performing a parameterized statistical static timing analysis (SSTA) of an integrated circuit taking into account setup and hold margin interdependence Oct 23, 2011 Issued
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