Search

John D. Blanton

Examiner (ID: 12088)

Most Active Art Unit
2466
Art Unit(s)
2466, 2619, 2419
Total Applications
1157
Issued Applications
871
Pending Applications
78
Abandoned Applications
233

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8765999 [patent_doc_number] => 20130094035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-18 [patent_title] => 'MULTIPLE PATTERNING TECHNOLOGY METHOD AND SYSTEM FOR ACHIEVING MINIMAL PATTERN MISMATCH' [patent_app_type] => utility [patent_app_number] => 13/275899 [patent_app_country] => US [patent_app_date] => 2011-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7682 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13275899 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/275899
Multiple patterning technology method and system for achieving minimal pattern mismatch Oct 17, 2011 Issued
Array ( [id] => 10589221 [patent_doc_number] => 09310831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-12 [patent_title] => 'Multi-mode multi-corner clocktree synthesis' [patent_app_type] => utility [patent_app_number] => 13/274276 [patent_app_country] => US [patent_app_date] => 2011-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4605 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13274276 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/274276
Multi-mode multi-corner clocktree synthesis Oct 13, 2011 Issued
Array ( [id] => 8757174 [patent_doc_number] => 20130091479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-11 [patent_title] => 'Parameter Matching Hotspot Detection' [patent_app_type] => utility [patent_app_number] => 13/267874 [patent_app_country] => US [patent_app_date] => 2011-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5297 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13267874 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/267874
Parameter matching hotspot detection Oct 5, 2011 Issued
Array ( [id] => 8189473 [patent_doc_number] => 20120117518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-10 [patent_title] => 'DESIGNING SYNTHETIC BIOLOGICAL CIRCUITS USING OPTIMALITY AND NONEQUILIBRIUM THERMODYNAMICS' [patent_app_type] => utility [patent_app_number] => 13/250043 [patent_app_country] => US [patent_app_date] => 2011-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 11610 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20120117518.pdf [firstpage_image] =>[orig_patent_app_number] => 13250043 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/250043
Designing synthetic biological circuits using optimality and nonequilibrium thermodynamics Sep 29, 2011 Issued
Array ( [id] => 9660981 [patent_doc_number] => 08807948 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-19 [patent_title] => 'System and method for automated real-time design checking' [patent_app_type] => utility [patent_app_number] => 13/248914 [patent_app_country] => US [patent_app_date] => 2011-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9068 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13248914 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/248914
System and method for automated real-time design checking Sep 28, 2011 Issued
Array ( [id] => 8925577 [patent_doc_number] => 20130181337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-18 [patent_title] => 'Power Routing with Integrated Decoupling Capacitance' [patent_app_type] => utility [patent_app_number] => 13/876303 [patent_app_country] => US [patent_app_date] => 2011-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3408 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13876303 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/876303
Power routing with integrated decoupling capacitance Sep 27, 2011 Issued
Array ( [id] => 9143594 [patent_doc_number] => 08584076 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-12 [patent_title] => 'Printed circuit board design assisting device, method, and program' [patent_app_type] => utility [patent_app_number] => 13/238613 [patent_app_country] => US [patent_app_date] => 2011-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 30 [patent_no_of_words] => 10900 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13238613 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/238613
Printed circuit board design assisting device, method, and program Sep 20, 2011 Issued
Array ( [id] => 8419102 [patent_doc_number] => 20120246602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-27 [patent_title] => 'METHOD OF PREPARING PATTERN, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND COMPUTER PROGRAM PRODUCT' [patent_app_type] => utility [patent_app_number] => 13/237663 [patent_app_country] => US [patent_app_date] => 2011-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6142 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13237663 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/237663
METHOD OF PREPARING PATTERN, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND COMPUTER PROGRAM PRODUCT Sep 19, 2011 Abandoned
Array ( [id] => 8935805 [patent_doc_number] => 08495527 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-23 [patent_title] => 'Pattern recognition with edge correction for design based metrology' [patent_app_type] => utility [patent_app_number] => 13/236698 [patent_app_country] => US [patent_app_date] => 2011-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 6075 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13236698 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/236698
Pattern recognition with edge correction for design based metrology Sep 19, 2011 Issued
Array ( [id] => 8051819 [patent_doc_number] => 20120075643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-29 [patent_title] => 'Method of revising printing error in PCB' [patent_app_type] => utility [patent_app_number] => 13/137878 [patent_app_country] => US [patent_app_date] => 2011-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3659 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20120075643.pdf [firstpage_image] =>[orig_patent_app_number] => 13137878 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/137878
Method of revising printing error in PCB Sep 19, 2011 Abandoned
Array ( [id] => 8325985 [patent_doc_number] => 20120198396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-02 [patent_title] => 'METHOD OF OPTIMIZING SEMICONDUCTOR DEVICE MANUFACTURING PROCESS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND NON-TRANSITORY COMPUTER READABLE MEDIUM' [patent_app_type] => utility [patent_app_number] => 13/237854 [patent_app_country] => US [patent_app_date] => 2011-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6430 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13237854 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/237854
METHOD OF OPTIMIZING SEMICONDUCTOR DEVICE MANUFACTURING PROCESS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND NON-TRANSITORY COMPUTER READABLE MEDIUM Sep 19, 2011 Abandoned
Array ( [id] => 8705474 [patent_doc_number] => 20130062763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-14 [patent_title] => 'DE-POP ON-DEVICE DECOUPLING FOR BGA' [patent_app_type] => utility [patent_app_number] => 13/231609 [patent_app_country] => US [patent_app_date] => 2011-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1977 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13231609 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/231609
De-pop on-device decoupling for BGA Sep 12, 2011 Issued
Array ( [id] => 9116335 [patent_doc_number] => 08572527 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-29 [patent_title] => 'Generating properties for circuit designs' [patent_app_type] => utility [patent_app_number] => 13/231583 [patent_app_country] => US [patent_app_date] => 2011-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 8285 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13231583 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/231583
Generating properties for circuit designs Sep 12, 2011 Issued
Array ( [id] => 8985273 [patent_doc_number] => 08516403 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'Multiple patterning layout decomposition for ease of conflict removal' [patent_app_type] => utility [patent_app_number] => 13/223844 [patent_app_country] => US [patent_app_date] => 2011-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 4822 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13223844 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/223844
Multiple patterning layout decomposition for ease of conflict removal Aug 31, 2011 Issued
Array ( [id] => 8699181 [patent_doc_number] => 20130061190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-07 [patent_title] => 'IDENTIFYING SPEED BINNING TEST VECTORS DURING SIMULATION OF AN INTEGRATED CIRCUIT DESIGN' [patent_app_type] => utility [patent_app_number] => 13/223423 [patent_app_country] => US [patent_app_date] => 2011-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5286 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13223423 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/223423
Identifying speed binning test vectors during simulation of an integrated circuit design Aug 31, 2011 Issued
Array ( [id] => 9063002 [patent_doc_number] => 08549457 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-01 [patent_title] => 'Method and system for implementing core placement' [patent_app_type] => utility [patent_app_number] => 13/219553 [patent_app_country] => US [patent_app_date] => 2011-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 6611 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13219553 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/219553
Method and system for implementing core placement Aug 25, 2011 Issued
Array ( [id] => 9358751 [patent_doc_number] => 08677307 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-03-18 [patent_title] => 'Method and system for implementing die size adjustment and visualization' [patent_app_type] => utility [patent_app_number] => 13/219534 [patent_app_country] => US [patent_app_date] => 2011-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5431 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13219534 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/219534
Method and system for implementing die size adjustment and visualization Aug 25, 2011 Issued
Array ( [id] => 8924085 [patent_doc_number] => 08490034 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-07-16 [patent_title] => 'Techniques of optical proximity correction using GPU' [patent_app_type] => utility [patent_app_number] => 13/178883 [patent_app_country] => US [patent_app_date] => 2011-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 34 [patent_no_of_words] => 30905 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13178883 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/178883
Techniques of optical proximity correction using GPU Jul 7, 2011 Issued
Array ( [id] => 8588862 [patent_doc_number] => 20130007683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'REDUCING OBSERVABILITY OF MEMORY ELEMENTS IN CIRCUITS' [patent_app_type] => utility [patent_app_number] => 13/175854 [patent_app_country] => US [patent_app_date] => 2011-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5387 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13175854 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/175854
Reducing observability of memory elements in circuits Jul 2, 2011 Issued
Array ( [id] => 9187243 [patent_doc_number] => 08627244 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-07 [patent_title] => 'Frequency domain layout decomposition in double patterning lithography' [patent_app_type] => utility [patent_app_number] => 13/171513 [patent_app_country] => US [patent_app_date] => 2011-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5304 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13171513 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/171513
Frequency domain layout decomposition in double patterning lithography Jun 28, 2011 Issued
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