Search

John D. Blanton

Examiner (ID: 12088)

Most Active Art Unit
2466
Art Unit(s)
2466, 2619, 2419
Total Applications
1157
Issued Applications
871
Pending Applications
78
Abandoned Applications
233

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18281842 [patent_doc_number] => 20230097314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => VERIFICATION OF HARDWARE DESIGN FOR COMPONENT THAT EVALUATES AN ALGEBRAIC EXPRESSION USING DECOMPOSITION AND RECOMBINATION [patent_app_type] => utility [patent_app_number] => 18/076338 [patent_app_country] => US [patent_app_date] => 2022-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19012 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18076338 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/076338
Verification of hardware design for component that evaluates an algebraic expression using decomposition and recombination Dec 5, 2022 Issued
Array ( [id] => 18271559 [patent_doc_number] => 20230092801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => POWER DISPLAY METHOD AND APPARATUS, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/994098 [patent_app_country] => US [patent_app_date] => 2022-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11460 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17994098 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/994098
POWER DISPLAY METHOD AND APPARATUS, AND ELECTRONIC DEVICE Nov 24, 2022 Pending
Array ( [id] => 19190223 [patent_doc_number] => 20240169136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => AUTOMATED POWER DISCRETE AND MODULE MODEL GENERATION FOR SYSTEM LEVEL SIMULATORS [patent_app_type] => utility [patent_app_number] => 18/058382 [patent_app_country] => US [patent_app_date] => 2022-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6747 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18058382 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/058382
AUTOMATED POWER DISCRETE AND MODULE MODEL GENERATION FOR SYSTEM LEVEL SIMULATORS Nov 22, 2022 Pending
Array ( [id] => 20345142 [patent_doc_number] => 12468874 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Method and system for using deep learning to improve design verification by optimizing code coverage, functional coverage, and bug detection [patent_app_type] => utility [patent_app_number] => 17/989805 [patent_app_country] => US [patent_app_date] => 2022-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7270 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17989805 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/989805
Method and system for using deep learning to improve design verification by optimizing code coverage, functional coverage, and bug detection Nov 17, 2022 Issued
Array ( [id] => 19021369 [patent_doc_number] => 20240077540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => ELECTRONIC DEVICE AND METHOD FOR CALIBRATING RSOC OF A BATTERY [patent_app_type] => utility [patent_app_number] => 18/056760 [patent_app_country] => US [patent_app_date] => 2022-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4662 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18056760 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/056760
ELECTRONIC DEVICE AND METHOD FOR CALIBRATING RSOC OF A BATTERY Nov 17, 2022 Pending
Array ( [id] => 18987213 [patent_doc_number] => 20240059182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => BATTERY CONTROL SYSTEMS AND METHODS BASED ON DERATED STATE OF VEHICLE [patent_app_type] => utility [patent_app_number] => 17/986382 [patent_app_country] => US [patent_app_date] => 2022-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13855 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17986382 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/986382
BATTERY CONTROL SYSTEMS AND METHODS BASED ON DERATED STATE OF VEHICLE Nov 13, 2022 Pending
Array ( [id] => 19022197 [patent_doc_number] => 20240078368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => METHODS AND APPARATUS TO GENERATE CIRCUIT TIMING CONSTRAINT PREDICTIONS USING MACHINE LEARNING [patent_app_type] => utility [patent_app_number] => 17/984053 [patent_app_country] => US [patent_app_date] => 2022-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15077 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17984053 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/984053
METHODS AND APPARATUS TO GENERATE CIRCUIT TIMING CONSTRAINT PREDICTIONS USING MACHINE LEARNING Nov 8, 2022 Pending
Array ( [id] => 18861164 [patent_doc_number] => 20230415599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => System for Charging Mobile Vehicle and Method for Charging Thereof [patent_app_type] => utility [patent_app_number] => 17/983202 [patent_app_country] => US [patent_app_date] => 2022-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5333 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17983202 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/983202
System for Charging Mobile Vehicle and Method for Charging Thereof Nov 7, 2022 Pending
Array ( [id] => 18363611 [patent_doc_number] => 20230145202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => POWER INTEGRATION SYSTEM WITH MOTOR DRIVE AND BATTERY CHARGING AND DISCHARGING FUNCTION [patent_app_type] => utility [patent_app_number] => 17/981605 [patent_app_country] => US [patent_app_date] => 2022-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4563 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17981605 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/981605
POWER INTEGRATION SYSTEM WITH MOTOR DRIVE AND BATTERY CHARGING AND DISCHARGING FUNCTION Nov 6, 2022 Pending
Array ( [id] => 20718502 [patent_doc_number] => 12633765 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-19 [patent_title] => Method for analyzing the contact assignment of a contact element of a cell module for a vehicle battery and module charger having a diagnosis function for the contact assignment of a contact element [patent_app_type] => utility [patent_app_number] => 17/979865 [patent_app_country] => US [patent_app_date] => 2022-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 0 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17979865 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/979865
METHOD FOR ANALYZING THE CONTACT ASSIGNMENT OF A CONTACT ELEMENT OF A CELL MODULE FOR A VEHICLE BATTERY AND MODULE CHARGER HAVING A DIAGNOSIS FUNCTION FOR THE CONTACT ASSIGNMENT OF A CONTACT ELEMENT Nov 2, 2022 Issued
Array ( [id] => 20358981 [patent_doc_number] => 12474976 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Computation of weakly connected components in a parallel, scalable and deterministic manner [patent_app_type] => utility [patent_app_number] => 17/974412 [patent_app_country] => US [patent_app_date] => 2022-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17974412 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/974412
Computation of weakly connected components in a parallel, scalable and deterministic manner Oct 25, 2022 Issued
Array ( [id] => 18228931 [patent_doc_number] => 20230067925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => REDUCED STANDBY CURRENT IN A MULTI-BATTERY WEARABLE DEVICE [patent_app_type] => utility [patent_app_number] => 18/047200 [patent_app_country] => US [patent_app_date] => 2022-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8409 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18047200 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/047200
Reduced standby current in a multi-battery wearable device Oct 16, 2022 Issued
Array ( [id] => 18438708 [patent_doc_number] => 20230186003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => DIGITAL DESIGN SIMULATION ACCELERATOR [patent_app_type] => utility [patent_app_number] => 17/960742 [patent_app_country] => US [patent_app_date] => 2022-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17960742 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/960742
DIGITAL DESIGN SIMULATION ACCELERATOR Oct 4, 2022 Pending
Array ( [id] => 18267562 [patent_doc_number] => 20230088804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => LEARNING-BASED ANALYZER FOR MITIGATING LATCH-UP IN INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/958930 [patent_app_country] => US [patent_app_date] => 2022-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9405 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17958930 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/958930
Learning-based analyzer for mitigating latch-up in integrated circuits Oct 2, 2022 Issued
Array ( [id] => 20494487 [patent_doc_number] => 12536359 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Decoupling capacitor parameter determination for a power distribution network [patent_app_type] => utility [patent_app_number] => 17/958249 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2187 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17958249 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/958249
Decoupling capacitor parameter determination for a power distribution network Sep 29, 2022 Issued
Array ( [id] => 18147615 [patent_doc_number] => 20230021472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => METHOD TO AVOID MEMORY BANK CONFLICTS AND PIPELINE CONFLICTS IN TENSOR MEMORY LAYOUT [patent_app_type] => utility [patent_app_number] => 17/954695 [patent_app_country] => US [patent_app_date] => 2022-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10197 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17954695 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/954695
Method to avoid memory bank conflicts and pipeline conflicts in tensor memory layout Sep 27, 2022 Issued
Array ( [id] => 20596679 [patent_doc_number] => 12580406 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-17 [patent_title] => Optimizing battery charging with synchronized context data [patent_app_type] => utility [patent_app_number] => 17/933712 [patent_app_country] => US [patent_app_date] => 2022-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 9866 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17933712 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/933712
Optimizing battery charging with synchronized context data Sep 19, 2022 Issued
Array ( [id] => 20610253 [patent_doc_number] => 12585855 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-24 [patent_title] => Method of designing layout of semiconductor integrated circuit, method of designing and manufacturing semiconductor integrated circuit using the same, and design system performing same [patent_app_type] => utility [patent_app_number] => 17/945724 [patent_app_country] => US [patent_app_date] => 2022-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 32 [patent_no_of_words] => 8999 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17945724 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/945724
Method of designing layout of semiconductor integrated circuit, method of designing and manufacturing semiconductor integrated circuit using the same, and design system performing same Sep 14, 2022 Issued
Array ( [id] => 20298388 [patent_doc_number] => 20250323631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-16 [patent_title] => METHODS AND APPARATUSES RELATING TO HYBRID MULTI-BIT FLIP-FLOPS [patent_app_type] => utility [patent_app_number] => 17/945984 [patent_app_country] => US [patent_app_date] => 2022-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17945984 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/945984
METHODS AND APPARATUSES RELATING TO HYBRID MULTI-BIT FLIP-FLOPS Sep 14, 2022 Pending
Array ( [id] => 18255964 [patent_doc_number] => 20230083003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => OPTICAL PATH TRACING IN AN OPTICAL CIRCUIT DESIGN [patent_app_type] => utility [patent_app_number] => 17/942003 [patent_app_country] => US [patent_app_date] => 2022-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11176 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17942003 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/942003
Optical path tracing in an optical circuit design Sep 8, 2022 Issued
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