
John D. Blanton
Examiner (ID: 12088)
| Most Active Art Unit | 2466 |
| Art Unit(s) | 2466, 2619, 2419 |
| Total Applications | 1157 |
| Issued Applications | 871 |
| Pending Applications | 78 |
| Abandoned Applications | 233 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6332820
[patent_doc_number] => 20100115485
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-05-06
[patent_title] => 'Circuit design device for conducting failure analysis facilitating design'
[patent_app_type] => utility
[patent_app_number] => 12/588991
[patent_app_country] => US
[patent_app_date] => 2009-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 11062
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0115/20100115485.pdf
[firstpage_image] =>[orig_patent_app_number] => 12588991
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/588991 | Circuit design device for conducting failure analysis facilitating design | Nov 3, 2009 | Issued |
Array
(
[id] => 8805036
[patent_doc_number] => 08443319
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-05-14
[patent_title] => 'Method for preparing re-architected designs for sequential equivalence checking'
[patent_app_type] => utility
[patent_app_number] => 13/128153
[patent_app_country] => US
[patent_app_date] => 2009-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 33
[patent_no_of_words] => 10939
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 316
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13128153
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/128153 | Method for preparing re-architected designs for sequential equivalence checking | Oct 27, 2009 | Issued |
Array
(
[id] => 6535232
[patent_doc_number] => 20100218147
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-08-26
[patent_title] => 'CIRCUIT SPECIFICATION DESCRIPTION VISUALIZING DEVICE, CIRCUIT SPECIFICATION DESCRIPTION VISUALIZING METHOD AND STORAGE MEDIUM'
[patent_app_type] => utility
[patent_app_number] => 12/578659
[patent_app_country] => US
[patent_app_date] => 2009-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 11690
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0218/20100218147.pdf
[firstpage_image] =>[orig_patent_app_number] => 12578659
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/578659 | Circuit specification description visualizing device, circuit specification description visualizing method and storage medium | Oct 13, 2009 | Issued |
Array
(
[id] => 6513130
[patent_doc_number] => 20100095262
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-04-15
[patent_title] => 'Schematic Generation From Analog Netlists'
[patent_app_type] => utility
[patent_app_number] => 12/574645
[patent_app_country] => US
[patent_app_date] => 2009-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 5344
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0095/20100095262.pdf
[firstpage_image] =>[orig_patent_app_number] => 12574645
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/574645 | Schematic generation visualization aid for netlists comprising analog circuits | Oct 5, 2009 | Issued |
Array
(
[id] => 8149415
[patent_doc_number] => 08166433
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-04-24
[patent_title] => 'Method to inspect floating connection and floating net of integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 12/493425
[patent_app_country] => US
[patent_app_date] => 2009-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2219
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/166/08166433.pdf
[firstpage_image] =>[orig_patent_app_number] => 12493425
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/493425 | Method to inspect floating connection and floating net of integrated circuit | Jun 28, 2009 | Issued |
Array
(
[id] => 8546515
[patent_doc_number] => 08321818
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-11-27
[patent_title] => 'Model-based retargeting of layout patterns for sub-wavelength photolithography'
[patent_app_type] => utility
[patent_app_number] => 12/492301
[patent_app_country] => US
[patent_app_date] => 2009-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 6700
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 302
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12492301
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/492301 | Model-based retargeting of layout patterns for sub-wavelength photolithography | Jun 25, 2009 | Issued |
Array
(
[id] => 8536238
[patent_doc_number] => 08312404
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-11-13
[patent_title] => 'Multi-segments modeling bond wire interconnects with 2D simulations in high speed, high density wire bond packages'
[patent_app_type] => utility
[patent_app_number] => 12/492198
[patent_app_country] => US
[patent_app_date] => 2009-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 18
[patent_no_of_words] => 8935
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 207
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12492198
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/492198 | Multi-segments modeling bond wire interconnects with 2D simulations in high speed, high density wire bond packages | Jun 25, 2009 | Issued |
Array
(
[id] => 5466701
[patent_doc_number] => 20090326901
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-31
[patent_title] => 'APPARATUS AND METHOD FOR ESTIMATING CHANGE AMOUNT IN REGISTER TRANSFER LEVEL STRUCTURE AND COMPUTER-READABLE RECORDING MEDIUM'
[patent_app_type] => utility
[patent_app_number] => 12/490637
[patent_app_country] => US
[patent_app_date] => 2009-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 9912
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0326/20090326901.pdf
[firstpage_image] =>[orig_patent_app_number] => 12490637
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/490637 | APPARATUS AND METHOD FOR ESTIMATING CHANGE AMOUNT IN REGISTER TRANSFER LEVEL STRUCTURE AND COMPUTER-READABLE RECORDING MEDIUM | Jun 23, 2009 | Abandoned |
Array
(
[id] => 8366767
[patent_doc_number] => 08255851
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-08-28
[patent_title] => 'Method and system for timing design'
[patent_app_type] => utility
[patent_app_number] => 12/490758
[patent_app_country] => US
[patent_app_date] => 2009-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7210
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12490758
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/490758 | Method and system for timing design | Jun 23, 2009 | Issued |
Array
(
[id] => 6628113
[patent_doc_number] => 20100324878
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-12-23
[patent_title] => 'METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING HOTSPOT DETECTION, REPAIR, AND OPTIMIZATION OF AN ELECTRONIC CIRCUIT DESIGN'
[patent_app_type] => utility
[patent_app_number] => 12/490245
[patent_app_country] => US
[patent_app_date] => 2009-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 14154
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0324/20100324878.pdf
[firstpage_image] =>[orig_patent_app_number] => 12490245
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/490245 | Methods, systems, and computer program product for implementing hotspot detection, repair, and optimization of an electronic circuit design | Jun 22, 2009 | Issued |
Array
(
[id] => 6644199
[patent_doc_number] => 20100313070
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-12-09
[patent_title] => 'BROKEN-SPHERES METHODOLOGY FOR IMPROVED FAILURE PROBABILITY ANALYSIS IN MULTI-FAIL REGIONS'
[patent_app_type] => utility
[patent_app_number] => 12/477361
[patent_app_country] => US
[patent_app_date] => 2009-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5519
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0313/20100313070.pdf
[firstpage_image] =>[orig_patent_app_number] => 12477361
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/477361 | Broken-spheres methodology for improved failure probability analysis in multi-fail regions | Jun 2, 2009 | Issued |
Array
(
[id] => 8546520
[patent_doc_number] => 08321824
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-11-27
[patent_title] => 'Multiple-power-domain static timing analysis'
[patent_app_type] => utility
[patent_app_number] => 12/433184
[patent_app_country] => US
[patent_app_date] => 2009-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7488
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12433184
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/433184 | Multiple-power-domain static timing analysis | Apr 29, 2009 | Issued |
Array
(
[id] => 6534552
[patent_doc_number] => 20100270671
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-10-28
[patent_title] => 'MANIPULATING FILL PATTERNS DURING ROUTING'
[patent_app_type] => utility
[patent_app_number] => 12/431154
[patent_app_country] => US
[patent_app_date] => 2009-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5238
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0270/20100270671.pdf
[firstpage_image] =>[orig_patent_app_number] => 12431154
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/431154 | MANIPULATING FILL PATTERNS DURING ROUTING | Apr 27, 2009 | Abandoned |
Array
(
[id] => 5486956
[patent_doc_number] => 20090276721
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-11-05
[patent_title] => 'METHOD AND APPARATUS FOR CONFIGURING A DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/427931
[patent_app_country] => US
[patent_app_date] => 2009-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 11458
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0276/20090276721.pdf
[firstpage_image] =>[orig_patent_app_number] => 12427931
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/427931 | METHOD AND APPARATUS FOR CONFIGURING A DEVICE | Apr 21, 2009 | Abandoned |
Array
(
[id] => 8536237
[patent_doc_number] => 08312402
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-11-13
[patent_title] => 'Method and apparatus for broadband electromagnetic modeling of three-dimensional interconnects embedded in multilayered substrates'
[patent_app_type] => utility
[patent_app_number] => 12/423714
[patent_app_country] => US
[patent_app_date] => 2009-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 22
[patent_no_of_words] => 19874
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 300
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12423714
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/423714 | Method and apparatus for broadband electromagnetic modeling of three-dimensional interconnects embedded in multilayered substrates | Apr 13, 2009 | Issued |
Array
(
[id] => 8461002
[patent_doc_number] => 08296689
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-10-23
[patent_title] => 'Customizing metal pattern density in die-stacking applications'
[patent_app_type] => utility
[patent_app_number] => 12/419234
[patent_app_country] => US
[patent_app_date] => 2009-04-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 4342
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12419234
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/419234 | Customizing metal pattern density in die-stacking applications | Apr 5, 2009 | Issued |
Array
(
[id] => 8195003
[patent_doc_number] => 08185864
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-05-22
[patent_title] => 'Circuit board analyzer and analysis method'
[patent_app_type] => utility
[patent_app_number] => 12/417214
[patent_app_country] => US
[patent_app_date] => 2009-04-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 32
[patent_no_of_words] => 11854
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/185/08185864.pdf
[firstpage_image] =>[orig_patent_app_number] => 12417214
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/417214 | Circuit board analyzer and analysis method | Apr 1, 2009 | Issued |
Array
(
[id] => 6281511
[patent_doc_number] => 20100257498
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-10-07
[patent_title] => 'INCREMENTAL TIMING OPTIMIZATION AND PLACEMENT'
[patent_app_type] => utility
[patent_app_number] => 12/416754
[patent_app_country] => US
[patent_app_date] => 2009-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6452
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0257/20100257498.pdf
[firstpage_image] =>[orig_patent_app_number] => 12416754
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/416754 | Incremental timing optimization and placement | Mar 31, 2009 | Issued |
Array
(
[id] => 6383174
[patent_doc_number] => 20100082313
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-04-01
[patent_title] => 'Optical Lithographic Process Model Calibration'
[patent_app_type] => utility
[patent_app_number] => 12/416044
[patent_app_country] => US
[patent_app_date] => 2009-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 8180
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0082/20100082313.pdf
[firstpage_image] =>[orig_patent_app_number] => 12416044
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/416044 | Optical Lithographic Process Model Calibration | Mar 30, 2009 | Abandoned |
Array
(
[id] => 6369639
[patent_doc_number] => 20100088656
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-04-08
[patent_title] => 'PROPERTY CHECKING SYSTEM, PROPERTY CHECKING METHOD, AND COMPUTER-READABLE STORAGE MEDIUM'
[patent_app_type] => utility
[patent_app_number] => 12/410614
[patent_app_country] => US
[patent_app_date] => 2009-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4674
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0088/20100088656.pdf
[firstpage_image] =>[orig_patent_app_number] => 12410614
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/410614 | PROPERTY CHECKING SYSTEM, PROPERTY CHECKING METHOD, AND COMPUTER-READABLE STORAGE MEDIUM | Mar 24, 2009 | Abandoned |