Search

John D. Blanton

Examiner (ID: 12088)

Most Active Art Unit
2466
Art Unit(s)
2466, 2619, 2419
Total Applications
1157
Issued Applications
871
Pending Applications
78
Abandoned Applications
233

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5476103 [patent_doc_number] => 20090249269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-01 [patent_title] => 'PROPERTY CHECKING SYSTEM, PROPERTY CHECKING METHOD, AND COMPUTER-READABLE STORAGE MEDIUM' [patent_app_type] => utility [patent_app_number] => 12/409860 [patent_app_country] => US [patent_app_date] => 2009-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4674 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0249/20090249269.pdf [firstpage_image] =>[orig_patent_app_number] => 12409860 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/409860
PROPERTY CHECKING SYSTEM, PROPERTY CHECKING METHOD, AND COMPUTER-READABLE STORAGE MEDIUM Mar 23, 2009 Abandoned
Array ( [id] => 5405768 [patent_doc_number] => 20090241083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'ROUTER-AIDED POST-PLACEMENT-AND-ROUTING-RETIMING' [patent_app_type] => utility [patent_app_number] => 12/406574 [patent_app_country] => US [patent_app_date] => 2009-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3934 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20090241083.pdf [firstpage_image] =>[orig_patent_app_number] => 12406574 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/406574
ROUTER-AIDED POST-PLACEMENT-AND-ROUTING-RETIMING Mar 17, 2009 Abandoned
Array ( [id] => 6587794 [patent_doc_number] => 20100235803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-16 [patent_title] => 'Method and Apparatus for Automatically Connecting Component Interfaces in a Model Description' [patent_app_type] => utility [patent_app_number] => 12/404844 [patent_app_country] => US [patent_app_date] => 2009-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10326 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20100235803.pdf [firstpage_image] =>[orig_patent_app_number] => 12404844 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/404844
Method and Apparatus for Automatically Connecting Component Interfaces in a Model Description Mar 15, 2009 Abandoned
Array ( [id] => 6652422 [patent_doc_number] => 20100229136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-09 [patent_title] => 'CROSSTALK TIME-DELAY ANALYSIS USING RANDOM VARIABLES' [patent_app_type] => utility [patent_app_number] => 12/399704 [patent_app_country] => US [patent_app_date] => 2009-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4730 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20100229136.pdf [firstpage_image] =>[orig_patent_app_number] => 12399704 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/399704
Crosstalk time-delay analysis using random variables Mar 5, 2009 Issued
Array ( [id] => 5525421 [patent_doc_number] => 20090195498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-06 [patent_title] => 'Signal Generator Providing ISI Scaling to Touchstone Files' [patent_app_type] => utility [patent_app_number] => 12/357298 [patent_app_country] => US [patent_app_date] => 2009-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5488 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20090195498.pdf [firstpage_image] =>[orig_patent_app_number] => 12357298 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/357298
Signal generator providing ISI scaling to touchstone files Jan 20, 2009 Issued
Array ( [id] => 8799633 [patent_doc_number] => 08438522 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-05-07 [patent_title] => 'Logic element architecture for generic logic chains in programmable devices' [patent_app_type] => utility [patent_app_number] => 12/237076 [patent_app_country] => US [patent_app_date] => 2008-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3677 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12237076 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/237076
Logic element architecture for generic logic chains in programmable devices Sep 23, 2008 Issued
Array ( [id] => 8530728 [patent_doc_number] => 08307312 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-06 [patent_title] => 'Simulation method of logic circuit' [patent_app_type] => utility [patent_app_number] => 12/190477 [patent_app_country] => US [patent_app_date] => 2008-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 3406 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12190477 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/190477
Simulation method of logic circuit Aug 11, 2008 Issued
Array ( [id] => 6376664 [patent_doc_number] => 20100316142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-16 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT AND DESIGNING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/514834 [patent_app_country] => US [patent_app_date] => 2008-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6871 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0316/20100316142.pdf [firstpage_image] =>[orig_patent_app_number] => 12514834 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/514834
SEMICONDUCTOR INTEGRATED CIRCUIT AND DESIGNING METHOD THEREOF Jul 6, 2008 Abandoned
Array ( [id] => 5405137 [patent_doc_number] => 20090240452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'SYSTEM AND METHOD FOR WIRELESS AND DYNAMIC INTRA-PROCESS MEASUREMENT OF INTEGRATED CIRCUIT PARAMETERS' [patent_app_type] => utility [patent_app_number] => 12/053705 [patent_app_country] => US [patent_app_date] => 2008-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7944 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20090240452.pdf [firstpage_image] =>[orig_patent_app_number] => 12053705 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/053705
System and method for wireless and dynamic intra-process measurement of integrated circuit parameters Mar 23, 2008 Issued
Array ( [id] => 6191293 [patent_doc_number] => 20110173577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-14 [patent_title] => 'Techniques for Pattern Process Tuning and Design Optimization for Maximizing Process-Sensitive Circuit Yields' [patent_app_type] => utility [patent_app_number] => 12/024390 [patent_app_country] => US [patent_app_date] => 2008-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4456 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20110173577.pdf [firstpage_image] =>[orig_patent_app_number] => 12024390 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/024390
Techniques for Pattern Process Tuning and Design Optimization for Maximizing Process-Sensitive Circuit Yields Jan 31, 2008 Abandoned
Array ( [id] => 8354711 [patent_doc_number] => 08250055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-21 [patent_title] => 'Non-linear dynamical search engine' [patent_app_type] => utility [patent_app_number] => 12/517959 [patent_app_country] => US [patent_app_date] => 2007-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 5624 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12517959 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/517959
Non-linear dynamical search engine Dec 4, 2007 Issued
Array ( [id] => 8810429 [patent_doc_number] => 08448096 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-05-21 [patent_title] => 'Method and system for parallel processing of IC design layouts' [patent_app_type] => utility [patent_app_number] => 11/479600 [patent_app_country] => US [patent_app_date] => 2006-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 11244 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11479600 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/479600
Method and system for parallel processing of IC design layouts Jun 29, 2006 Issued
Array ( [id] => 8899598 [patent_doc_number] => 08479132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-02 [patent_title] => 'Active trace assertion based verification system' [patent_app_type] => utility [patent_app_number] => 11/455134 [patent_app_country] => US [patent_app_date] => 2006-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 4948 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11455134 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/455134
Active trace assertion based verification system Jun 15, 2006 Issued
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