John D. Blanton

Array ( [id] => 18038727 [patent_doc_number] => 20220382943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => IDENTIFYING ASSOCIATION OF SAFETY RELATED PORTS TO THEIR SAFETY MECHANISMS THROUGH STRUCTURAL ANALYSIS [patent_app_type] => utility [patent_app_number] => 17/750809 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9003 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17750809 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18728240 [patent_doc_number] => 20230342533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => METHOD FOR INTRA-CELL-REPURPOSING DUMMY TRANSISTORS AND SEMICONDUCTOR DEVICE HAVING REPURPOSED FORMERLY DUMMY TRANSISTORS [patent_app_type] => utility [patent_app_number] => 17/743374 [patent_app_country] => US [patent_app_date] => 2022-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16403 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17743374 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18333453 [patent_doc_number] => 20230125401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => METHOD OF PREDICTING CHARACTERISTIC OF SEMICONDUCTOR DEVICE AND COMPUTING DEVICE PERFORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/741860 [patent_app_country] => US [patent_app_date] => 2022-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12629 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17741860 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20624215 [patent_doc_number] => 12591723 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-31 [patent_title] => Generating RTL for a circuit using DSP blocks [patent_app_type] => utility [patent_app_number] => 17/739409 [patent_app_country] => US [patent_app_date] => 2022-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 3377 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17739409 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18639958 [patent_doc_number] => 11764589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => System and method for controlling a high-voltage battery system [patent_app_type] => utility [patent_app_number] => 17/736313 [patent_app_country] => US [patent_app_date] => 2022-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4618 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17736313 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17796232 [patent_doc_number] => 20220255324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => EXTENDING SHELF LIFE OF RECHARGEABLE BATTERIES [patent_app_type] => utility [patent_app_number] => 17/660834 [patent_app_country] => US [patent_app_date] => 2022-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4168 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17660834 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18728239 [patent_doc_number] => 20230342532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => METHOD, NON-TRANSITORY COMPUTER-READABLE MEDIUM, AND APPARATUS FOR ARRANGING ELECTRICAL COMPONENTS WITHIN A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/729518 [patent_app_country] => US [patent_app_date] => 2022-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13388 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17729518 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17989653 [patent_doc_number] => 20220355690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => CHARGING SYSTEM FOR A FIRE FIGHTING VEHICLE [patent_app_type] => utility [patent_app_number] => 17/729796 [patent_app_country] => US [patent_app_date] => 2022-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21637 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17729796 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19956661 [patent_doc_number] => 12327076 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-10 [patent_title] => Method and system for monitoring clock duty cycles [patent_app_type] => utility [patent_app_number] => 17/728304 [patent_app_country] => US [patent_app_date] => 2022-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17728304 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18415125 [patent_doc_number] => 11669668 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Method for comprehensive integration verification of mixed-signal circuits [patent_app_type] => utility [patent_app_number] => 17/722445 [patent_app_country] => US [patent_app_date] => 2022-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5163 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17722445 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18711585 [patent_doc_number] => 20230334214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => DESIGN OF AN INTEGRATED CIRCUIT USING MULTIPLE AND DIFFERENT PROCESS CORNERS [patent_app_type] => utility [patent_app_number] => 17/722009 [patent_app_country] => US [patent_app_date] => 2022-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8878 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17722009 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20273998 [patent_doc_number] => 12443781 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Integrated thermal-electrical co-simulation [patent_app_type] => utility [patent_app_number] => 17/716527 [patent_app_country] => US [patent_app_date] => 2022-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 0 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17716527 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20188943 [patent_doc_number] => 12400058 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Method, system, medium and program for clock design of physical partition structure [patent_app_type] => utility [patent_app_number] => 17/709359 [patent_app_country] => US [patent_app_date] => 2022-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 8951 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17709359 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18212395 [patent_doc_number] => 20230058659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => WIRELESS CHARGING TABLE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/656995 [patent_app_country] => US [patent_app_date] => 2022-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9625 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17656995 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17950052 [patent_doc_number] => 20220337071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => INTEGRATED CHARGING DEVICE, CHARGING PILE AND METHOD FOR CONTROLLING CHARGING PILE [patent_app_type] => utility [patent_app_number] => 17/706439 [patent_app_country] => US [patent_app_date] => 2022-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8537 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17706439 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20304422 [patent_doc_number] => 12450415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Library design and co-optimization with a circuit design [patent_app_type] => utility [patent_app_number] => 17/705137 [patent_app_country] => US [patent_app_date] => 2022-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 3438 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17705137 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17722429 [patent_doc_number] => 20220215151 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => ELECTROMIGRATION EVALUATION METHODOLOGY WITH CONSIDERATION OF BOTH SELF-HEATING AND HEAT SINK THERMAL EFFECTS [patent_app_type] => utility [patent_app_number] => 17/702625 [patent_app_country] => US [patent_app_date] => 2022-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10156 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17702625 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20240348 [patent_doc_number] => 12420654 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Mount for a charging station [patent_app_type] => utility [patent_app_number] => 17/701282 [patent_app_country] => US [patent_app_date] => 2022-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17701282 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19872909 [patent_doc_number] => 12265771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Method for dividing simulation models up between a processor and an FPGA [patent_app_type] => utility [patent_app_number] => 17/697095 [patent_app_country] => US [patent_app_date] => 2022-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 7541 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17697095 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18532156 [patent_doc_number] => 20230237228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => COMPUTER READABLE RECORDING MEDIUM WITH STORED PROGRAM AND METHOD OF EXTRACTING PARASITIC PARAMETERS OF A 3D IC THEREOF [patent_app_type] => utility [patent_app_number] => 17/691127 [patent_app_country] => US [patent_app_date] => 2022-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2994 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17691127 [rel_patent_id] =>[rel_patent_doc_number] =>)