Search

John D Freeman

Examiner (ID: 17393, Phone: (571)270-3469 , Office: P/1787 )

Most Active Art Unit
1787
Art Unit(s)
4174, 1794, 1787
Total Applications
752
Issued Applications
292
Pending Applications
67
Abandoned Applications
393

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6765782 [patent_doc_number] => 20030100182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-29 [patent_title] => 'Method for formation of copper diffusion barrier film using aluminum' [patent_app_type] => new [patent_app_number] => 10/306491 [patent_app_country] => US [patent_app_date] => 2002-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1174 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20030100182.pdf [firstpage_image] =>[orig_patent_app_number] => 10306491 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/306491
Method for formation of copper diffusion barrier film using aluminum Nov 26, 2002 Issued
Array ( [id] => 6669007 [patent_doc_number] => 20030113991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-19 [patent_title] => 'Semiconductor device manufacturing method' [patent_app_type] => new [patent_app_number] => 10/307081 [patent_app_country] => US [patent_app_date] => 2002-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4098 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20030113991.pdf [firstpage_image] =>[orig_patent_app_number] => 10307081 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/307081
Semiconductor device manufacturing method Nov 26, 2002 Abandoned
Array ( [id] => 6649791 [patent_doc_number] => 20030104699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-05 [patent_title] => 'Slurry for chemical mechanical polishing for copper and method of manufacturing semiconductor device using the slurry' [patent_app_type] => new [patent_app_number] => 10/303855 [patent_app_country] => US [patent_app_date] => 2002-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4668 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20030104699.pdf [firstpage_image] =>[orig_patent_app_number] => 10303855 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/303855
Method of manufacturing a semiconductor device using a slurry for chemical mechanical polishing of copper Nov 25, 2002 Issued
Array ( [id] => 6676928 [patent_doc_number] => 20030227068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-11 [patent_title] => 'Sputtering target' [patent_app_type] => new [patent_app_number] => 10/297001 [patent_app_country] => US [patent_app_date] => 2002-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6936 [patent_no_of_claims] => 192 [patent_no_of_ind_claims] => 39 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20030227068.pdf [firstpage_image] =>[orig_patent_app_number] => 10297001 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/297001
Sputtering target Nov 25, 2002 Abandoned
Array ( [id] => 1050034 [patent_doc_number] => 06861311 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-01 [patent_title] => 'SEMICONDUCTOR PROCESSING METHODS OF FORMING INTEGRATED CIRCUITRY, FORMING CONDUCTIVE LINES, FORMING A CONDUCTIVE GRID, FORMING A CONDUCTIVE NETWORK, FORMING AN ELECTRICAL INTERCONNECTION TO A NODE LOCATION, FORMING AN ELECTRICAL INTERCONNECTION WITH A TRANSISTOR SOURCE/DRAIN REGION, AND INTEGRATED CIRCUITRY' [patent_app_type] => utility [patent_app_number] => 10/304359 [patent_app_country] => US [patent_app_date] => 2002-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 4977 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/861/06861311.pdf [firstpage_image] =>[orig_patent_app_number] => 10304359 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/304359
SEMICONDUCTOR PROCESSING METHODS OF FORMING INTEGRATED CIRCUITRY, FORMING CONDUCTIVE LINES, FORMING A CONDUCTIVE GRID, FORMING A CONDUCTIVE NETWORK, FORMING AN ELECTRICAL INTERCONNECTION TO A NODE LOCATION, FORMING AN ELECTRICAL INTERCONNECTION WITH A TRANSISTOR SOURCE/DRAIN REGION, AND INTEGRATED CIRCUITRY Nov 24, 2002 Issued
Array ( [id] => 6813756 [patent_doc_number] => 20030073306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'Semiconductor processing methods of forming integrated circuitry, forming conductive lines, forming a conductive grid, forming a conductive network, forming an electrical interconnection to a node location, forming an electrical interconnection with a transistor source/drain region, and integrated circuitry' [patent_app_type] => new [patent_app_number] => 10/304659 [patent_app_country] => US [patent_app_date] => 2002-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4905 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20030073306.pdf [firstpage_image] =>[orig_patent_app_number] => 10304659 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/304659
SEMICONDUCTOR PROCESSING METHODS OF FORMING INTEGRATED CIRCUITRY, FORMING CONDUCTIVE LINES, FORMING A CONDUCTIVE GRID, FORMING A CONDUCTIVE NETWORK, FORMING AN ELECTRICAL INTERCONNECTION TO A NODE LOCATION, FORMING AN ELECTRICAL INTERCONNECTION WITH A TRANSISTOR SOURCE/DRAIN REGION, AND INTEGRATED CIRCUITRY Nov 24, 2002 Issued
Array ( [id] => 6659737 [patent_doc_number] => 20030134502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-17 [patent_title] => 'Method for fabricating high aspect ratio electrodes' [patent_app_type] => new [patent_app_number] => 10/300801 [patent_app_country] => US [patent_app_date] => 2002-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4516 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20030134502.pdf [firstpage_image] =>[orig_patent_app_number] => 10300801 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/300801
Method for fabricating high aspect ratio electrodes Nov 20, 2002 Issued
Array ( [id] => 6813746 [patent_doc_number] => 20030073296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'A Method Of Forming At Least One Interconnection To A Source/Drain Region In Silicon-On-Insulator Integrated Circuitry' [patent_app_type] => new [patent_app_number] => 10/302044 [patent_app_country] => US [patent_app_date] => 2002-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4903 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20030073296.pdf [firstpage_image] =>[orig_patent_app_number] => 10302044 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/302044
Method of forming at least one interconnection to a source/drain region in silicon-on-insulator integrated circuitry Nov 20, 2002 Issued
Array ( [id] => 6813757 [patent_doc_number] => 20030073307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'Forming conductive layers on insulators by physical vapor deposition' [patent_app_type] => new [patent_app_number] => 10/300231 [patent_app_country] => US [patent_app_date] => 2002-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1611 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20030073307.pdf [firstpage_image] =>[orig_patent_app_number] => 10300231 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/300231
Forming conductive layers on insulators by physical vapor deposition Nov 18, 2002 Issued
Array ( [id] => 1017952 [patent_doc_number] => 06890846 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-10 [patent_title] => 'Method for manufacturing semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 10/293442 [patent_app_country] => US [patent_app_date] => 2002-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 27 [patent_no_of_words] => 21402 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/890/06890846.pdf [firstpage_image] =>[orig_patent_app_number] => 10293442 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/293442
Method for manufacturing semiconductor integrated circuit device Nov 13, 2002 Issued
Array ( [id] => 6656045 [patent_doc_number] => 20030132521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-17 [patent_title] => 'Method for electrical interconnection employing salicide bridge' [patent_app_type] => new [patent_app_number] => 10/292772 [patent_app_country] => US [patent_app_date] => 2002-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5284 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20030132521.pdf [firstpage_image] =>[orig_patent_app_number] => 10292772 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/292772
Method for electrical interconnection employing salicide bridge Nov 11, 2002 Issued
Array ( [id] => 1264325 [patent_doc_number] => 06660568 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-09 [patent_title] => 'BiLevel metallization for embedded back end of the line structures' [patent_app_type] => B1 [patent_app_number] => 10/290412 [patent_app_country] => US [patent_app_date] => 2002-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1591 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/660/06660568.pdf [firstpage_image] =>[orig_patent_app_number] => 10290412 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/290412
BiLevel metallization for embedded back end of the line structures Nov 6, 2002 Issued
Array ( [id] => 1299430 [patent_doc_number] => 06623995 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Optimized monitor method for a metal patterning process' [patent_app_type] => B1 [patent_app_number] => 10/283437 [patent_app_country] => US [patent_app_date] => 2002-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2198 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/623/06623995.pdf [firstpage_image] =>[orig_patent_app_number] => 10283437 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/283437
Optimized monitor method for a metal patterning process Oct 29, 2002 Issued
Array ( [id] => 6781177 [patent_doc_number] => 20030062624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-03 [patent_title] => 'Component built-in module and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/271937 [patent_app_country] => US [patent_app_date] => 2002-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12326 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20030062624.pdf [firstpage_image] =>[orig_patent_app_number] => 10271937 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/271937
Method of manufacturing a component built-in module Oct 14, 2002 Issued
Array ( [id] => 1264528 [patent_doc_number] => 06660630 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-09 [patent_title] => 'Method for forming a tapered dual damascene via portion with improved performance' [patent_app_type] => B1 [patent_app_number] => 10/268511 [patent_app_country] => US [patent_app_date] => 2002-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 3717 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/660/06660630.pdf [firstpage_image] =>[orig_patent_app_number] => 10268511 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/268511
Method for forming a tapered dual damascene via portion with improved performance Oct 9, 2002 Issued
Array ( [id] => 7033754 [patent_doc_number] => 20050032264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-10 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/492061 [patent_app_country] => US [patent_app_date] => 2002-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3925 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20050032264.pdf [firstpage_image] =>[orig_patent_app_number] => 10492061 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/492061
Method of manufacturing a semiconductor device with outline of cleave marking regions and alignment or registration features Oct 6, 2002 Issued
Array ( [id] => 968521 [patent_doc_number] => 06939795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-06 [patent_title] => 'Selective dry etching of tantalum and tantalum nitride' [patent_app_type] => utility [patent_app_number] => 10/253791 [patent_app_country] => US [patent_app_date] => 2002-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1340 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/939/06939795.pdf [firstpage_image] =>[orig_patent_app_number] => 10253791 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/253791
Selective dry etching of tantalum and tantalum nitride Sep 22, 2002 Issued
Array ( [id] => 6772453 [patent_doc_number] => 20030015791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-23 [patent_title] => 'Semiconductor device and method of fabrication thereof, semiconductor module, circuit board, and electronic equipment' [patent_app_type] => new [patent_app_number] => 10/244162 [patent_app_country] => US [patent_app_date] => 2002-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8676 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20030015791.pdf [firstpage_image] =>[orig_patent_app_number] => 10244162 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/244162
Semiconductor device and method of fabrication thereof, semiconductor module, circuit board, and electronic equipment Sep 15, 2002 Issued
Array ( [id] => 6659746 [patent_doc_number] => 20030134509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-17 [patent_title] => 'Manufacturing method of semiconductor device' [patent_app_type] => new [patent_app_number] => 10/242422 [patent_app_country] => US [patent_app_date] => 2002-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9379 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20030134509.pdf [firstpage_image] =>[orig_patent_app_number] => 10242422 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/242422
Manufacturing method of semiconductor device Sep 12, 2002 Issued
Array ( [id] => 7135178 [patent_doc_number] => 20040043582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Method and apparatus for simultaneously removing multiple conductive materials from microelectronic substrates' [patent_app_type] => new [patent_app_number] => 10/230602 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6126 [patent_no_of_claims] => 73 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20040043582.pdf [firstpage_image] =>[orig_patent_app_number] => 10230602 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/230602
Method for simultaneously removing multiple conductive materials from microelectronic substrates Aug 28, 2002 Issued
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