Search

John D Freeman

Examiner (ID: 17393, Phone: (571)270-3469 , Office: P/1787 )

Most Active Art Unit
1787
Art Unit(s)
4174, 1794, 1787
Total Applications
752
Issued Applications
292
Pending Applications
67
Abandoned Applications
393

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6755955 [patent_doc_number] => 20030003732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Method of post treatment for a metal line of semiconductor device' [patent_app_type] => new [patent_app_number] => 10/180735 [patent_app_country] => US [patent_app_date] => 2002-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1239 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20030003732.pdf [firstpage_image] =>[orig_patent_app_number] => 10180735 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/180735
Method of post treatment for a metal line of semiconductor device Jun 25, 2002 Abandoned
Array ( [id] => 6825361 [patent_doc_number] => 20030235983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-25 [patent_title] => 'Temperature control sequence of electroless plating baths' [patent_app_type] => new [patent_app_number] => 10/178053 [patent_app_country] => US [patent_app_date] => 2002-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6316 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20030235983.pdf [firstpage_image] =>[orig_patent_app_number] => 10178053 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/178053
Temperature control sequence of electroless plating baths Jun 20, 2002 Issued
Array ( [id] => 6674435 [patent_doc_number] => 20030060038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Forming interconnects' [patent_app_type] => new [patent_app_number] => 10/176173 [patent_app_country] => US [patent_app_date] => 2002-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 14574 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 25 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20030060038.pdf [firstpage_image] =>[orig_patent_app_number] => 10176173 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/176173
Forming interconnects using locally deposited solvents Jun 20, 2002 Issued
Array ( [id] => 1146605 [patent_doc_number] => 06774026 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-10 [patent_title] => 'Structure and method for low-stress concentration solder bumps' [patent_app_type] => B1 [patent_app_number] => 10/177912 [patent_app_country] => US [patent_app_date] => 2002-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1968 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/774/06774026.pdf [firstpage_image] =>[orig_patent_app_number] => 10177912 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/177912
Structure and method for low-stress concentration solder bumps Jun 19, 2002 Issued
Array ( [id] => 1397096 [patent_doc_number] => 06531387 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'Polishing of conductive layers in fabrication of integrated circuits' [patent_app_type] => B1 [patent_app_number] => 10/174431 [patent_app_country] => US [patent_app_date] => 2002-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2136 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/531/06531387.pdf [firstpage_image] =>[orig_patent_app_number] => 10174431 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/174431
Polishing of conductive layers in fabrication of integrated circuits Jun 16, 2002 Issued
Array ( [id] => 1196705 [patent_doc_number] => 06727172 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-27 [patent_title] => 'Process to reduce chemical mechanical polishing damage of narrow copper lines' [patent_app_type] => B1 [patent_app_number] => 10/170242 [patent_app_country] => US [patent_app_date] => 2002-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1798 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/727/06727172.pdf [firstpage_image] =>[orig_patent_app_number] => 10170242 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/170242
Process to reduce chemical mechanical polishing damage of narrow copper lines Jun 11, 2002 Issued
Array ( [id] => 1146623 [patent_doc_number] => 06774028 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-10 [patent_title] => 'Method of forming wiring structure by using photo resist having optimum development rate' [patent_app_type] => B2 [patent_app_number] => 10/166362 [patent_app_country] => US [patent_app_date] => 2002-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 43 [patent_no_of_words] => 10905 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/774/06774028.pdf [firstpage_image] =>[orig_patent_app_number] => 10166362 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/166362
Method of forming wiring structure by using photo resist having optimum development rate Jun 10, 2002 Issued
Array ( [id] => 1440097 [patent_doc_number] => 06495448 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Dual damascene process' [patent_app_type] => B1 [patent_app_number] => 10/165794 [patent_app_country] => US [patent_app_date] => 2002-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 1835 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/495/06495448.pdf [firstpage_image] =>[orig_patent_app_number] => 10165794 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/165794
Dual damascene process Jun 6, 2002 Issued
Array ( [id] => 1085658 [patent_doc_number] => 06831003 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-14 [patent_title] => 'Continuous barrier for interconnect structure formed in porous dielectric material with minimized electromigration' [patent_app_type] => B1 [patent_app_number] => 10/161451 [patent_app_country] => US [patent_app_date] => 2002-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 5365 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/831/06831003.pdf [firstpage_image] =>[orig_patent_app_number] => 10161451 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/161451
Continuous barrier for interconnect structure formed in porous dielectric material with minimized electromigration May 30, 2002 Issued
Array ( [id] => 1358456 [patent_doc_number] => 06573136 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-03 [patent_title] => 'Isolating a vertical gate contact structure' [patent_app_type] => B1 [patent_app_number] => 10/158982 [patent_app_country] => US [patent_app_date] => 2002-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2166 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/573/06573136.pdf [firstpage_image] =>[orig_patent_app_number] => 10158982 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/158982
Isolating a vertical gate contact structure May 29, 2002 Issued
Array ( [id] => 6745299 [patent_doc_number] => 20030022482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-30 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => new [patent_app_number] => 10/157402 [patent_app_country] => US [patent_app_date] => 2002-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2723 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20030022482.pdf [firstpage_image] =>[orig_patent_app_number] => 10157402 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/157402
Method of manufacturing a semiconductor device May 28, 2002 Issued
Array ( [id] => 6259078 [patent_doc_number] => 20020187266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-12 [patent_title] => 'Metal film pattern and manufacturing method thereof' [patent_app_type] => new [patent_app_number] => 10/151881 [patent_app_country] => US [patent_app_date] => 2002-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7700 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20020187266.pdf [firstpage_image] =>[orig_patent_app_number] => 10151881 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/151881
Method of making a metal film pattern May 21, 2002 Issued
Array ( [id] => 7631422 [patent_doc_number] => 06635510 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Method of making a parylene coating for soldermask' [patent_app_type] => B1 [patent_app_number] => 10/153372 [patent_app_country] => US [patent_app_date] => 2002-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 3582 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/635/06635510.pdf [firstpage_image] =>[orig_patent_app_number] => 10153372 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/153372
Method of making a parylene coating for soldermask May 21, 2002 Issued
Array ( [id] => 1130432 [patent_doc_number] => 06787436 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-07 [patent_title] => 'Silicide-silicon contacts for reduction of MOSFET source-drain resistances' [patent_app_type] => B1 [patent_app_number] => 10/147382 [patent_app_country] => US [patent_app_date] => 2002-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1788 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/787/06787436.pdf [firstpage_image] =>[orig_patent_app_number] => 10147382 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/147382
Silicide-silicon contacts for reduction of MOSFET source-drain resistances May 14, 2002 Issued
Array ( [id] => 1324341 [patent_doc_number] => 06602779 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-05 [patent_title] => 'Method for forming low dielectric constant damascene structure while employing carbon doped silicon oxide planarizing stop layer' [patent_app_type] => B1 [patent_app_number] => 10/144522 [patent_app_country] => US [patent_app_date] => 2002-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 5688 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/602/06602779.pdf [firstpage_image] =>[orig_patent_app_number] => 10144522 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/144522
Method for forming low dielectric constant damascene structure while employing carbon doped silicon oxide planarizing stop layer May 12, 2002 Issued
Array ( [id] => 1341592 [patent_doc_number] => 06586330 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-01 [patent_title] => 'Method for depositing conformal nitrified tantalum silicide films by thermal CVD' [patent_app_type] => B1 [patent_app_number] => 10/140538 [patent_app_country] => US [patent_app_date] => 2002-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 7034 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/586/06586330.pdf [firstpage_image] =>[orig_patent_app_number] => 10140538 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/140538
Method for depositing conformal nitrified tantalum silicide films by thermal CVD May 6, 2002 Issued
Array ( [id] => 6761406 [patent_doc_number] => 20030124768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-03 [patent_title] => 'WAFER LEVEL PACKAGING AND CHIP STRUCTURE' [patent_app_type] => new [patent_app_number] => 10/063572 [patent_app_country] => US [patent_app_date] => 2002-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3436 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20030124768.pdf [firstpage_image] =>[orig_patent_app_number] => 10063572 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/063572
Method of making wafer level packaging and chip structure May 2, 2002 Issued
Array ( [id] => 1416568 [patent_doc_number] => 06518185 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Integration scheme for non-feature-size dependent cu-alloy introduction' [patent_app_type] => B1 [patent_app_number] => 10/127521 [patent_app_country] => US [patent_app_date] => 2002-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 2147 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/518/06518185.pdf [firstpage_image] =>[orig_patent_app_number] => 10127521 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/127521
Integration scheme for non-feature-size dependent cu-alloy introduction Apr 21, 2002 Issued
10/123751 Method of ultra-low energy ion implantation to form alloy layers in copper Apr 15, 2002 Pending
Array ( [id] => 1281190 [patent_doc_number] => 06642146 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-04 [patent_title] => 'Method of depositing copper seed on semiconductor substrates' [patent_app_type] => B1 [patent_app_number] => 10/121949 [patent_app_country] => US [patent_app_date] => 2002-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 28 [patent_no_of_words] => 12802 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/642/06642146.pdf [firstpage_image] =>[orig_patent_app_number] => 10121949 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/121949
Method of depositing copper seed on semiconductor substrates Apr 9, 2002 Issued
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