Search

John D Freeman

Examiner (ID: 17393, Phone: (571)270-3469 , Office: P/1787 )

Most Active Art Unit
1787
Art Unit(s)
4174, 1794, 1787
Total Applications
752
Issued Applications
292
Pending Applications
67
Abandoned Applications
393

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7645659 [patent_doc_number] => 06472310 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Tin palladium activation with maximized nuclei density and uniformity on barrier material in interconnect structure' [patent_app_type] => B1 [patent_app_number] => 10/118511 [patent_app_country] => US [patent_app_date] => 2002-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 4891 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/472/06472310.pdf [firstpage_image] =>[orig_patent_app_number] => 10118511 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/118511
Tin palladium activation with maximized nuclei density and uniformity on barrier material in interconnect structure Apr 7, 2002 Issued
Array ( [id] => 963632 [patent_doc_number] => 06949444 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-27 [patent_title] => 'High-frequency line' [patent_app_type] => utility [patent_app_number] => 10/117782 [patent_app_country] => US [patent_app_date] => 2002-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 3683 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/949/06949444.pdf [firstpage_image] =>[orig_patent_app_number] => 10117782 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/117782
High-frequency line Apr 4, 2002 Issued
Array ( [id] => 1332550 [patent_doc_number] => 06596629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-22 [patent_title] => 'Method for forming wire in semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/116941 [patent_app_country] => US [patent_app_date] => 2002-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2267 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/596/06596629.pdf [firstpage_image] =>[orig_patent_app_number] => 10116941 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/116941
Method for forming wire in semiconductor device Apr 4, 2002 Issued
Array ( [id] => 1134412 [patent_doc_number] => 06784092 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-31 [patent_title] => 'Method of forming insulating film and method of manufacturing semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/105432 [patent_app_country] => US [patent_app_date] => 2002-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4485 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/784/06784092.pdf [firstpage_image] =>[orig_patent_app_number] => 10105432 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/105432
Method of forming insulating film and method of manufacturing semiconductor device Mar 25, 2002 Issued
Array ( [id] => 6539332 [patent_doc_number] => 20020137276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Method for forming contact having low resistivity using porous plug and method for forming semiconductor devices using the same' [patent_app_type] => new [patent_app_number] => 10/103942 [patent_app_country] => US [patent_app_date] => 2002-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6730 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20020137276.pdf [firstpage_image] =>[orig_patent_app_number] => 10103942 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/103942
Method for forming contact having low resistivity using porous plug and method for forming semiconductor devices using the same Mar 21, 2002 Abandoned
Array ( [id] => 6796553 [patent_doc_number] => 20030175427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-18 [patent_title] => 'Forming nanoscale patterned thin film metal layers' [patent_app_type] => new [patent_app_number] => 10/098202 [patent_app_country] => US [patent_app_date] => 2002-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4999 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20030175427.pdf [firstpage_image] =>[orig_patent_app_number] => 10098202 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/098202
Forming nanoscale patterned thin film metal layers Mar 14, 2002 Issued
Array ( [id] => 1155921 [patent_doc_number] => 06764952 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-20 [patent_title] => 'Systems and methods to retard copper diffusion and improve film adhesion for a dielectric barrier on copper' [patent_app_type] => B1 [patent_app_number] => 10/099232 [patent_app_country] => US [patent_app_date] => 2002-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3812 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/764/06764952.pdf [firstpage_image] =>[orig_patent_app_number] => 10099232 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/099232
Systems and methods to retard copper diffusion and improve film adhesion for a dielectric barrier on copper Mar 12, 2002 Issued
Array ( [id] => 6745303 [patent_doc_number] => 20030022486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-30 [patent_title] => 'Method for preventing shorts between contact windows and metal lines' [patent_app_type] => new [patent_app_number] => 10/097052 [patent_app_country] => US [patent_app_date] => 2002-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 1554 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20030022486.pdf [firstpage_image] =>[orig_patent_app_number] => 10097052 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/097052
Method for preventing shorts between contact windows and metal lines Mar 12, 2002 Abandoned
Array ( [id] => 6713084 [patent_doc_number] => 20030024431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'Electroless plating solution and method of forming wiring with the same' [patent_app_type] => new [patent_app_number] => 09/890455 [patent_app_country] => US [patent_app_date] => 2002-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2656 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20030024431.pdf [firstpage_image] =>[orig_patent_app_number] => 09890455 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/890455
Electroless plating solution and method of forming wiring with the same Mar 11, 2002 Abandoned
Array ( [id] => 1062818 [patent_doc_number] => 06849562 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-01 [patent_title] => 'Method of depositing a low k dielectric barrier film for copper damascene application' [patent_app_type] => utility [patent_app_number] => 10/092203 [patent_app_country] => US [patent_app_date] => 2002-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2712 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/849/06849562.pdf [firstpage_image] =>[orig_patent_app_number] => 10092203 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/092203
Method of depositing a low k dielectric barrier film for copper damascene application Mar 3, 2002 Issued
Array ( [id] => 1264535 [patent_doc_number] => 06660633 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-09 [patent_title] => 'Method of reducing electromigration in a copper line by electroplating an interim copper-zinc alloy thin film on a copper surface and a semiconductor device thereby formed' [patent_app_type] => B1 [patent_app_number] => 10/083809 [patent_app_country] => US [patent_app_date] => 2002-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 6111 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/660/06660633.pdf [firstpage_image] =>[orig_patent_app_number] => 10083809 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/083809
Method of reducing electromigration in a copper line by electroplating an interim copper-zinc alloy thin film on a copper surface and a semiconductor device thereby formed Feb 25, 2002 Issued
Array ( [id] => 1151930 [patent_doc_number] => 06767782 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-27 [patent_title] => 'Manufacturing method of semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/082311 [patent_app_country] => US [patent_app_date] => 2002-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 39 [patent_no_of_words] => 10444 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/767/06767782.pdf [firstpage_image] =>[orig_patent_app_number] => 10082311 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/082311
Manufacturing method of semiconductor device Feb 25, 2002 Issued
Array ( [id] => 1354874 [patent_doc_number] => 06576548 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-10 [patent_title] => 'Method of manufacturing a semiconductor device with reliable contacts/vias' [patent_app_type] => B1 [patent_app_number] => 10/079861 [patent_app_country] => US [patent_app_date] => 2002-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2413 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/576/06576548.pdf [firstpage_image] =>[orig_patent_app_number] => 10079861 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/079861
Method of manufacturing a semiconductor device with reliable contacts/vias Feb 21, 2002 Issued
Array ( [id] => 1188859 [patent_doc_number] => 06734090 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-11 [patent_title] => 'Method of making an edge seal for a semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/078861 [patent_app_country] => US [patent_app_date] => 2002-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 4050 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/734/06734090.pdf [firstpage_image] =>[orig_patent_app_number] => 10078861 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/078861
Method of making an edge seal for a semiconductor device Feb 19, 2002 Issued
Array ( [id] => 1264509 [patent_doc_number] => 06660624 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-09 [patent_title] => 'Method for reducing fluorine induced defects on a bonding pad surface' [patent_app_type] => B2 [patent_app_number] => 10/076891 [patent_app_country] => US [patent_app_date] => 2002-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 2784 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/660/06660624.pdf [firstpage_image] =>[orig_patent_app_number] => 10076891 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/076891
Method for reducing fluorine induced defects on a bonding pad surface Feb 13, 2002 Issued
Array ( [id] => 6427888 [patent_doc_number] => 20020175424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Process of forming metal surfaces compatible with a wire bonding and semiconductor integrated circuits manufactured by the process' [patent_app_type] => new [patent_app_number] => 10/078243 [patent_app_country] => US [patent_app_date] => 2002-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4471 [patent_no_of_claims] => 78 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20020175424.pdf [firstpage_image] =>[orig_patent_app_number] => 10078243 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/078243
Process of forming metal surfaces compatible with a wire bonding and semiconductor integrated circuits manufactured by the process Feb 13, 2002 Abandoned
Array ( [id] => 1394849 [patent_doc_number] => 06541378 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-01 [patent_title] => 'Low-temperature HDI fabrication' [patent_app_type] => B1 [patent_app_number] => 10/075684 [patent_app_country] => US [patent_app_date] => 2002-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 6354 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/541/06541378.pdf [firstpage_image] =>[orig_patent_app_number] => 10075684 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/075684
Low-temperature HDI fabrication Feb 12, 2002 Issued
Array ( [id] => 1386510 [patent_doc_number] => 06548398 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Production method of semiconductor device and production device therefor' [patent_app_type] => B1 [patent_app_number] => 10/049282 [patent_app_country] => US [patent_app_date] => 2002-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7640 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/548/06548398.pdf [firstpage_image] =>[orig_patent_app_number] => 10049282 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/049282
Production method of semiconductor device and production device therefor Feb 10, 2002 Issued
Array ( [id] => 1209391 [patent_doc_number] => 06713382 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'Vapor treatment for repairing damage of low-k dielectric' [patent_app_type] => B1 [patent_app_number] => 10/059268 [patent_app_country] => US [patent_app_date] => 2002-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 5421 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/713/06713382.pdf [firstpage_image] =>[orig_patent_app_number] => 10059268 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/059268
Vapor treatment for repairing damage of low-k dielectric Jan 30, 2002 Issued
Array ( [id] => 1500405 [patent_doc_number] => 06486054 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Method to achieve robust solder bump height' [patent_app_type] => B1 [patent_app_number] => 10/058472 [patent_app_country] => US [patent_app_date] => 2002-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 1640 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/486/06486054.pdf [firstpage_image] =>[orig_patent_app_number] => 10058472 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/058472
Method to achieve robust solder bump height Jan 27, 2002 Issued
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