Search

John D Freeman

Examiner (ID: 17393, Phone: (571)270-3469 , Office: P/1787 )

Most Active Art Unit
1787
Art Unit(s)
4174, 1794, 1787
Total Applications
752
Issued Applications
292
Pending Applications
67
Abandoned Applications
393

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5843717 [patent_doc_number] => 20020132042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-19 [patent_title] => 'Plating catalysts' [patent_app_type] => new [patent_app_number] => 10/000981 [patent_app_country] => US [patent_app_date] => 2001-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5574 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20020132042.pdf [firstpage_image] =>[orig_patent_app_number] => 10000981 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/000981
Plating catalysts Oct 23, 2001 Issued
Array ( [id] => 1574753 [patent_doc_number] => 06468893 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-22 [patent_title] => 'Method of forming solder bumps' [patent_app_type] => B2 [patent_app_number] => 10/047172 [patent_app_country] => US [patent_app_date] => 2001-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 11379 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/468/06468893.pdf [firstpage_image] =>[orig_patent_app_number] => 10047172 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/047172
Method of forming solder bumps Oct 22, 2001 Issued
Array ( [id] => 6657162 [patent_doc_number] => 20030077849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-24 [patent_title] => 'Method for fabricating ohmic contact layer in semiconductor devices' [patent_app_type] => new [patent_app_number] => 10/055221 [patent_app_country] => US [patent_app_date] => 2001-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2080 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20030077849.pdf [firstpage_image] =>[orig_patent_app_number] => 10055221 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/055221
Method for fabricating ohmic contact layer in semiconductor devices Oct 18, 2001 Abandoned
Array ( [id] => 1424469 [patent_doc_number] => 06503824 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Forming conductive layers on insulators by physical vapor deposition' [patent_app_type] => B1 [patent_app_number] => 09/976392 [patent_app_country] => US [patent_app_date] => 2001-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1587 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/503/06503824.pdf [firstpage_image] =>[orig_patent_app_number] => 09976392 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/976392
Forming conductive layers on insulators by physical vapor deposition Oct 11, 2001 Issued
Array ( [id] => 1196695 [patent_doc_number] => 06727167 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-27 [patent_title] => 'Method of making an aligned electrode on a semiconductor structure' [patent_app_type] => B2 [patent_app_number] => 09/976342 [patent_app_country] => US [patent_app_date] => 2001-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 6215 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/727/06727167.pdf [firstpage_image] =>[orig_patent_app_number] => 09976342 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/976342
Method of making an aligned electrode on a semiconductor structure Oct 11, 2001 Issued
Array ( [id] => 1341632 [patent_doc_number] => 06586334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-01 [patent_title] => 'Reducing copper line resistivity by smoothing trench and via sidewalls' [patent_app_type] => B2 [patent_app_number] => 09/975571 [patent_app_country] => US [patent_app_date] => 2001-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 2068 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/586/06586334.pdf [firstpage_image] =>[orig_patent_app_number] => 09975571 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/975571
Reducing copper line resistivity by smoothing trench and via sidewalls Oct 10, 2001 Issued
Array ( [id] => 6685491 [patent_doc_number] => 20030029212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-13 [patent_title] => 'Method and apparatus for processing thin metal layers' [patent_app_type] => new [patent_app_number] => 10/129159 [patent_app_country] => US [patent_app_date] => 2002-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 54 [patent_no_of_words] => 26464 [patent_no_of_claims] => 88 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20030029212.pdf [firstpage_image] =>[orig_patent_app_number] => 10129159 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/129159
Method and apparatus for processing thin metal layers Oct 8, 2001 Issued
Array ( [id] => 1068729 [patent_doc_number] => 06844255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-18 [patent_title] => 'Methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry' [patent_app_type] => utility [patent_app_number] => 10/011212 [patent_app_country] => US [patent_app_date] => 2001-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2655 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/844/06844255.pdf [firstpage_image] =>[orig_patent_app_number] => 10011212 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/011212
Methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry Oct 8, 2001 Issued
Array ( [id] => 1315557 [patent_doc_number] => 06607977 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-19 [patent_title] => 'Method of depositing a diffusion barrier for copper interconnect applications' [patent_app_type] => B1 [patent_app_number] => 09/965472 [patent_app_country] => US [patent_app_date] => 2001-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 7894 [patent_no_of_claims] => 73 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/607/06607977.pdf [firstpage_image] =>[orig_patent_app_number] => 09965472 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/965472
Method of depositing a diffusion barrier for copper interconnect applications Sep 25, 2001 Issued
Array ( [id] => 679659 [patent_doc_number] => 07084027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'Method for producing an integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/399985 [patent_app_country] => US [patent_app_date] => 2001-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2327 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/084/07084027.pdf [firstpage_image] =>[orig_patent_app_number] => 10399985 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/399985
Method for producing an integrated circuit Sep 17, 2001 Issued
Array ( [id] => 1424592 [patent_doc_number] => 06503835 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Method of making an organic copper diffusion barrier layer' [patent_app_type] => B1 [patent_app_number] => 09/939606 [patent_app_country] => US [patent_app_date] => 2001-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2489 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/503/06503835.pdf [firstpage_image] =>[orig_patent_app_number] => 09939606 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/939606
Method of making an organic copper diffusion barrier layer Aug 27, 2001 Issued
Array ( [id] => 1302680 [patent_doc_number] => 06620654 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-16 [patent_title] => 'Method for fabricating a simplified CMOS polysilicon thin film transistor and resulting structure' [patent_app_type] => B2 [patent_app_number] => 09/941200 [patent_app_country] => US [patent_app_date] => 2001-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 30 [patent_no_of_words] => 3595 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/620/06620654.pdf [firstpage_image] =>[orig_patent_app_number] => 09941200 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/941200
Method for fabricating a simplified CMOS polysilicon thin film transistor and resulting structure Aug 27, 2001 Issued
Array ( [id] => 1402314 [patent_doc_number] => 06534403 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-18 [patent_title] => 'Method of making a contact and via structure' [patent_app_type] => B2 [patent_app_number] => 09/939321 [patent_app_country] => US [patent_app_date] => 2001-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 26 [patent_no_of_words] => 8756 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/534/06534403.pdf [firstpage_image] =>[orig_patent_app_number] => 09939321 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/939321
Method of making a contact and via structure Aug 23, 2001 Issued
Array ( [id] => 6686109 [patent_doc_number] => 20030029832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-13 [patent_title] => 'Method for forming large integration and ultra-fine lines on a substrate' [patent_app_type] => new [patent_app_number] => 09/927515 [patent_app_country] => US [patent_app_date] => 2001-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1472 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20030029832.pdf [firstpage_image] =>[orig_patent_app_number] => 09927515 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/927515
Method for forming large integration and ultra-fine lines on a substrate Aug 12, 2001 Abandoned
Array ( [id] => 6395712 [patent_doc_number] => 20020036309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-28 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => new [patent_app_number] => 09/924120 [patent_app_country] => US [patent_app_date] => 2001-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9429 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20020036309.pdf [firstpage_image] =>[orig_patent_app_number] => 09924120 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/924120
Semiconductor device and method for fabricating the same Aug 7, 2001 Abandoned
Array ( [id] => 1318108 [patent_doc_number] => 06605479 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-12 [patent_title] => 'Method of using damaged areas of a wafer for process qualifications and experiments, and system for accomplishing same' [patent_app_type] => B1 [patent_app_number] => 09/917327 [patent_app_country] => US [patent_app_date] => 2001-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4221 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/605/06605479.pdf [firstpage_image] =>[orig_patent_app_number] => 09917327 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/917327
Method of using damaged areas of a wafer for process qualifications and experiments, and system for accomplishing same Jul 26, 2001 Issued
Array ( [id] => 1346360 [patent_doc_number] => 06583031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-24 [patent_title] => 'Method of making a MEMS element having perpendicular portion formed from substrate' [patent_app_type] => B2 [patent_app_number] => 09/915217 [patent_app_country] => US [patent_app_date] => 2001-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 6585 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/583/06583031.pdf [firstpage_image] =>[orig_patent_app_number] => 09915217 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/915217
Method of making a MEMS element having perpendicular portion formed from substrate Jul 24, 2001 Issued
Array ( [id] => 1602633 [patent_doc_number] => 06432812 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Method of coupling capacitance reduction' [patent_app_type] => B1 [patent_app_number] => 09/906331 [patent_app_country] => US [patent_app_date] => 2001-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 6 [patent_no_of_words] => 1945 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/432/06432812.pdf [firstpage_image] =>[orig_patent_app_number] => 09906331 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/906331
Method of coupling capacitance reduction Jul 15, 2001 Issued
Array ( [id] => 7643910 [patent_doc_number] => 06429128 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Method of forming nitride capped Cu lines with reduced electromigration along the Cu/nitride interface' [patent_app_type] => B1 [patent_app_number] => 09/902587 [patent_app_country] => US [patent_app_date] => 2001-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 6128 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/429/06429128.pdf [firstpage_image] =>[orig_patent_app_number] => 09902587 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/902587
Method of forming nitride capped Cu lines with reduced electromigration along the Cu/nitride interface Jul 11, 2001 Issued
Array ( [id] => 5801680 [patent_doc_number] => 20020009878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-24 [patent_title] => 'Method for manufacturing a multilayer interconnection structure' [patent_app_type] => new [patent_app_number] => 09/901682 [patent_app_country] => US [patent_app_date] => 2001-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4646 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20020009878.pdf [firstpage_image] =>[orig_patent_app_number] => 09901682 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/901682
Method for manufacturing a multilayer interconnection structure Jul 10, 2001 Issued
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