John D Freeman

Array ( [id] => 1458872 [patent_doc_number] => 06426287 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-07-30 [patent_title] => 'Method for forming a semiconductor connection with a top surface having an enlarged recess' [patent_app_type] => B2 [patent_app_number] => 09/903338 [patent_app_country] => US [patent_app_date] => 2001-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3589 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/426/06426287.pdf [firstpage_image] =>[orig_patent_app_number] => 09903338 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6884927 [patent_doc_number] => 20010039089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-08 [patent_title] => 'Memory array having a digit line buried in an isolation region and method for forming same' [patent_app_type] => new [patent_app_number] => 09/900341 [patent_app_country] => US [patent_app_date] => 2001-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 6507 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20010039089.pdf [firstpage_image] =>[orig_patent_app_number] => 09900341 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6503509 [patent_doc_number] => 20020025670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-28 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => new [patent_app_number] => 09/897472 [patent_app_country] => US [patent_app_date] => 2001-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9829 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20020025670.pdf [firstpage_image] =>[orig_patent_app_number] => 09897472 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1399454 [patent_doc_number] => 06537913 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-25 [patent_title] => 'Method of making a semiconductor device with aluminum capped copper interconnect pads' [patent_app_type] => B2 [patent_app_number] => 09/895522 [patent_app_country] => US [patent_app_date] => 2001-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2503 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/537/06537913.pdf [firstpage_image] =>[orig_patent_app_number] => 09895522 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1440095 [patent_doc_number] => 06495447 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Use of hydrogen doping for protection of low-k dielectric layers' [patent_app_type] => B1 [patent_app_number] => 09/888431 [patent_app_country] => US [patent_app_date] => 2001-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 5385 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/495/06495447.pdf [firstpage_image] =>[orig_patent_app_number] => 09888431 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1534625 [patent_doc_number] => 06489230 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Integration of low-k SiOF as inter-layer dielectric' [patent_app_type] => B1 [patent_app_number] => 09/886032 [patent_app_country] => US [patent_app_date] => 2001-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 4106 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/489/06489230.pdf [firstpage_image] =>[orig_patent_app_number] => 09886032 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5888718 [patent_doc_number] => 20020013046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-31 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/884074 [patent_app_country] => US [patent_app_date] => 2001-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2967 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20020013046.pdf [firstpage_image] =>[orig_patent_app_number] => 09884074 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1595694 [patent_doc_number] => 06492258 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25-M AND SMALLER SEMICONDUCTOR CHIP TECHNOLOGY BY ANNEALING INTERCONNECT LINES AND USING LOW BIAS VOLTAGE AND LOW INTERLAYER DIELECTRIC DEPOSITION RATE AND SEMICONDUCTOR CHIP MADE THEREBY' [patent_app_type] => B1 [patent_app_number] => 09/881831 [patent_app_country] => US [patent_app_date] => 2001-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2929 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/492/06492258.pdf [firstpage_image] =>[orig_patent_app_number] => 09881831 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6260780 [patent_doc_number] => 20020187653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-12 [patent_title] => 'Method of forming a spin-on-passivation layer' [patent_app_type] => new [patent_app_number] => 09/878361 [patent_app_country] => US [patent_app_date] => 2001-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2044 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20020187653.pdf [firstpage_image] =>[orig_patent_app_number] => 09878361 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7643989 [patent_doc_number] => 06429049 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Laser method for forming vias' [patent_app_type] => B1 [patent_app_number] => 09/874154 [patent_app_country] => US [patent_app_date] => 2001-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 2691 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 8 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/429/06429049.pdf [firstpage_image] =>[orig_patent_app_number] => 09874154 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1376314 [patent_doc_number] => 06559048 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Method of making a sloped sidewall via for integrated circuit structure to suppress via poisoning' [patent_app_type] => B1 [patent_app_number] => 09/870851 [patent_app_country] => US [patent_app_date] => 2001-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4273 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/559/06559048.pdf [firstpage_image] =>[orig_patent_app_number] => 09870851 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1550494 [patent_doc_number] => 06399493 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Method of silicide formation by silicon pretreatment' [patent_app_type] => B1 [patent_app_number] => 09/860141 [patent_app_country] => US [patent_app_date] => 2001-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3027 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/399/06399493.pdf [firstpage_image] =>[orig_patent_app_number] => 09860141 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1485354 [patent_doc_number] => 06365506 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Dual-damascene process with porous low-K dielectric material' [patent_app_type] => B1 [patent_app_number] => 09/859762 [patent_app_country] => US [patent_app_date] => 2001-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 2202 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/365/06365506.pdf [firstpage_image] =>[orig_patent_app_number] => 09859762 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1500363 [patent_doc_number] => 06486045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-26 [patent_title] => 'Apparatus and method for forming deposited film' [patent_app_type] => B2 [patent_app_number] => 09/851552 [patent_app_country] => US [patent_app_date] => 2001-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 7402 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/486/06486045.pdf [firstpage_image] =>[orig_patent_app_number] => 09851552 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1602643 [patent_doc_number] => 06432822 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Method of improving electromigration resistance of capped Cu' [patent_app_type] => B1 [patent_app_number] => 09/846611 [patent_app_country] => US [patent_app_date] => 2001-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4160 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/432/06432822.pdf [firstpage_image] =>[orig_patent_app_number] => 09846611 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7631361 [patent_doc_number] => 06635571 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-21 [patent_title] => 'Process for forming aluminum or aluminum oxide thin film on substrates' [patent_app_type] => B2 [patent_app_number] => 09/841072 [patent_app_country] => US [patent_app_date] => 2001-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2101 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 12 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/635/06635571.pdf [firstpage_image] =>[orig_patent_app_number] => 09841072 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1462637 [patent_doc_number] => 06350689 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Method to remove copper contamination by using downstream oxygen and chelating agent plasma' [patent_app_type] => B1 [patent_app_number] => 09/839962 [patent_app_country] => US [patent_app_date] => 2001-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2048 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/350/06350689.pdf [firstpage_image] =>[orig_patent_app_number] => 09839962 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1585627 [patent_doc_number] => 06358843 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Method of making ultra small vias for integrated circuits' [patent_app_type] => B1 [patent_app_number] => 09/824421 [patent_app_country] => US [patent_app_date] => 2001-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2483 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/358/06358843.pdf [firstpage_image] =>[orig_patent_app_number] => 09824421 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6427735 [patent_doc_number] => 20020175413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Method for utilizing tungsten barrier in contacts to silicide and structure produced therby' [patent_app_type] => new [patent_app_number] => 09/820591 [patent_app_country] => US [patent_app_date] => 2001-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2807 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20020175413.pdf [firstpage_image] =>[orig_patent_app_number] => 09820591 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6540055 [patent_doc_number] => 20020137331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Method of forming contact holes of reduced dimensions by using reverse-transcription process' [patent_app_type] => new [patent_app_number] => 09/813051 [patent_app_country] => US [patent_app_date] => 2001-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2141 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20020137331.pdf [firstpage_image] =>[orig_patent_app_number] => 09813051 [rel_patent_id] =>[rel_patent_doc_number] =>)