Search

John D Freeman

Examiner (ID: 17393, Phone: (571)270-3469 , Office: P/1787 )

Most Active Art Unit
1787
Art Unit(s)
4174, 1794, 1787
Total Applications
752
Issued Applications
292
Pending Applications
67
Abandoned Applications
393

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1585637 [patent_doc_number] => 06358845 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Method for forming inter metal dielectric' [patent_app_type] => B1 [patent_app_number] => 09/808921 [patent_app_country] => US [patent_app_date] => 2001-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2330 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/358/06358845.pdf [firstpage_image] =>[orig_patent_app_number] => 09808921 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/808921
Method for forming inter metal dielectric Mar 15, 2001 Issued
Array ( [id] => 1550490 [patent_doc_number] => 06399492 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Ruthenium silicide processing methods' [patent_app_type] => B1 [patent_app_number] => 09/810008 [patent_app_country] => US [patent_app_date] => 2001-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2368 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/399/06399492.pdf [firstpage_image] =>[orig_patent_app_number] => 09810008 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/810008
Ruthenium silicide processing methods Mar 14, 2001 Issued
Array ( [id] => 1495035 [patent_doc_number] => 06403466 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Post-CMP-Cu deposition and CMP to eliminate surface voids' [patent_app_type] => B1 [patent_app_number] => 09/805651 [patent_app_country] => US [patent_app_date] => 2001-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3391 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/403/06403466.pdf [firstpage_image] =>[orig_patent_app_number] => 09805651 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/805651
Post-CMP-Cu deposition and CMP to eliminate surface voids Mar 12, 2001 Issued
Array ( [id] => 6435245 [patent_doc_number] => 20020127849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'Method of manufacturing dual damascene structure' [patent_app_type] => new [patent_app_number] => 09/802508 [patent_app_country] => US [patent_app_date] => 2001-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2027 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20020127849.pdf [firstpage_image] =>[orig_patent_app_number] => 09802508 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/802508
Method of manufacturing dual damascene structure Mar 8, 2001 Abandoned
Array ( [id] => 1435920 [patent_doc_number] => 06355563 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Versatile copper-wiring layout design with low-k dielectric integration' [patent_app_type] => B1 [patent_app_number] => 09/798652 [patent_app_country] => US [patent_app_date] => 2001-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 2605 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/355/06355563.pdf [firstpage_image] =>[orig_patent_app_number] => 09798652 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/798652
Versatile copper-wiring layout design with low-k dielectric integration Mar 4, 2001 Issued
Array ( [id] => 7014575 [patent_doc_number] => 20010051421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-13 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => new [patent_app_number] => 09/794621 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6154 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20010051421.pdf [firstpage_image] =>[orig_patent_app_number] => 09794621 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/794621
Method of manufacturing a bump electrode semiconductor device using photosensitive resin Feb 27, 2001 Issued
Array ( [id] => 1459525 [patent_doc_number] => 06391766 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Method of making a slot via filled dual damascene structure with middle stop layer' [patent_app_type] => B1 [patent_app_number] => 09/788641 [patent_app_country] => US [patent_app_date] => 2001-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 5091 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/391/06391766.pdf [firstpage_image] =>[orig_patent_app_number] => 09788641 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/788641
Method of making a slot via filled dual damascene structure with middle stop layer Feb 20, 2001 Issued
Array ( [id] => 1550437 [patent_doc_number] => 06399478 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-06-04 [patent_title] => 'Method of making a dual damascene structure with modified insulation' [patent_app_type] => B2 [patent_app_number] => 09/788661 [patent_app_country] => US [patent_app_date] => 2001-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 3143 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/399/06399478.pdf [firstpage_image] =>[orig_patent_app_number] => 09788661 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/788661
Method of making a dual damascene structure with modified insulation Feb 20, 2001 Issued
Array ( [id] => 1485351 [patent_doc_number] => 06365505 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Method of making a slot via filled dual damascene structure with middle stop layer' [patent_app_type] => B1 [patent_app_number] => 09/780531 [patent_app_country] => US [patent_app_date] => 2001-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 5286 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/365/06365505.pdf [firstpage_image] =>[orig_patent_app_number] => 09780531 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/780531
Method of making a slot via filled dual damascene structure with middle stop layer Feb 20, 2001 Issued
Array ( [id] => 6060418 [patent_doc_number] => 20020030280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-14 [patent_title] => 'Semiconductor device having dual damascene line structure and method for fabricating the same' [patent_app_type] => new [patent_app_number] => 09/780830 [patent_app_country] => US [patent_app_date] => 2001-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4199 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20020030280.pdf [firstpage_image] =>[orig_patent_app_number] => 09780830 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/780830
Method of making a semiconductor device having dual damascene line structure using a patterned etching stopper Feb 8, 2001 Issued
Array ( [id] => 1542727 [patent_doc_number] => 06372631 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Method of making a via filled dual damascene structure without middle stop layer' [patent_app_type] => B1 [patent_app_number] => 09/778061 [patent_app_country] => US [patent_app_date] => 2001-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4883 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/372/06372631.pdf [firstpage_image] =>[orig_patent_app_number] => 09778061 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/778061
Method of making a via filled dual damascene structure without middle stop layer Feb 6, 2001 Issued
Array ( [id] => 7643917 [patent_doc_number] => 06429121 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Method of fabricating dual damascene with silicon carbide via mask/ARC' [patent_app_type] => B1 [patent_app_number] => 09/778102 [patent_app_country] => US [patent_app_date] => 2001-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3198 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/429/06429121.pdf [firstpage_image] =>[orig_patent_app_number] => 09778102 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/778102
Method of fabricating dual damascene with silicon carbide via mask/ARC Feb 6, 2001 Issued
Array ( [id] => 6876100 [patent_doc_number] => 20010006253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-05 [patent_title] => 'Components with releasable leads and methods of making releasable leads' [patent_app_type] => new-utility [patent_app_number] => 09/777781 [patent_app_country] => US [patent_app_date] => 2001-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5876 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20010006253.pdf [firstpage_image] =>[orig_patent_app_number] => 09777781 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/777781
Components with releasable leads and methods of making releasable leads Feb 5, 2001 Issued
Array ( [id] => 1474662 [patent_doc_number] => 06387807 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Method for selective removal of copper' [patent_app_type] => B1 [patent_app_number] => 09/772722 [patent_app_country] => US [patent_app_date] => 2001-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 8205 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/387/06387807.pdf [firstpage_image] =>[orig_patent_app_number] => 09772722 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/772722
Method for selective removal of copper Jan 29, 2001 Issued
Array ( [id] => 1478101 [patent_doc_number] => 06451664 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Method of making a MIM capacitor with self-passivating plates' [patent_app_type] => B1 [patent_app_number] => 09/774251 [patent_app_country] => US [patent_app_date] => 2001-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 5005 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/451/06451664.pdf [firstpage_image] =>[orig_patent_app_number] => 09774251 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/774251
Method of making a MIM capacitor with self-passivating plates Jan 29, 2001 Issued
Array ( [id] => 1476405 [patent_doc_number] => 06388322 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Article comprising a mechanically compliant bump' [patent_app_type] => B1 [patent_app_number] => 09/764192 [patent_app_country] => US [patent_app_date] => 2001-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 6014 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388322.pdf [firstpage_image] =>[orig_patent_app_number] => 09764192 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/764192
Article comprising a mechanically compliant bump Jan 16, 2001 Issued
Array ( [id] => 1458848 [patent_doc_number] => 06426281 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Method to form bump in bumping technology' [patent_app_type] => B1 [patent_app_number] => 09/759911 [patent_app_country] => US [patent_app_date] => 2001-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 5918 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 402 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/426/06426281.pdf [firstpage_image] =>[orig_patent_app_number] => 09759911 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/759911
Method to form bump in bumping technology Jan 15, 2001 Issued
Array ( [id] => 1549841 [patent_doc_number] => 06346477 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Method of interlayer mediated epitaxy of cobalt silicide from low temperature chemical vapor deposition of cobalt' [patent_app_type] => B1 [patent_app_number] => 09/757201 [patent_app_country] => US [patent_app_date] => 2001-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8291 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/346/06346477.pdf [firstpage_image] =>[orig_patent_app_number] => 09757201 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/757201
Method of interlayer mediated epitaxy of cobalt silicide from low temperature chemical vapor deposition of cobalt Jan 8, 2001 Issued
Array ( [id] => 6986891 [patent_doc_number] => 20010036723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-01 [patent_title] => 'Method of forming insulated metal interconnections in integrated circuits' [patent_app_type] => new [patent_app_number] => 09/742891 [patent_app_country] => US [patent_app_date] => 2000-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2643 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20010036723.pdf [firstpage_image] =>[orig_patent_app_number] => 09742891 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/742891
Method of forming insulated metal interconnections in integrated circuits Dec 19, 2000 Issued
Array ( [id] => 1559839 [patent_doc_number] => 06436811 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Method of forming a copper-containing metal interconnect using a chemical mechanical planarization (CMP) slurry' [patent_app_type] => B1 [patent_app_number] => 09/741131 [patent_app_country] => US [patent_app_date] => 2000-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9283 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/436/06436811.pdf [firstpage_image] =>[orig_patent_app_number] => 09741131 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/741131
Method of forming a copper-containing metal interconnect using a chemical mechanical planarization (CMP) slurry Dec 18, 2000 Issued
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