Application number | Title of the application | Filing Date | Status |
---|
Array
(
[id] => 6122422
[patent_doc_number] => 20020074234
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-20
[patent_title] => 'METHOD OF COPPER ELECTROPLATING'
[patent_app_type] => new
[patent_app_number] => 09/739930
[patent_app_country] => US
[patent_app_date] => 2000-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3556
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0074/20020074234.pdf
[firstpage_image] =>[orig_patent_app_number] => 09739930
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/739930 | Method of copper electroplating | Dec 17, 2000 | Issued |
Array
(
[id] => 1346876
[patent_doc_number] => 06579738
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-06-17
[patent_title] => 'Method of alignment for buried structures formed by surface transformation of empty spaces in solid state materials'
[patent_app_type] => B2
[patent_app_number] => 09/736247
[patent_app_country] => US
[patent_app_date] => 2000-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 21
[patent_no_of_words] => 6577
[patent_no_of_claims] => 50
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/579/06579738.pdf
[firstpage_image] =>[orig_patent_app_number] => 09736247
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/736247 | Method of alignment for buried structures formed by surface transformation of empty spaces in solid state materials | Dec 14, 2000 | Issued |
Array
(
[id] => 1416129
[patent_doc_number] => 06509213
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-01-21
[patent_title] => 'Methods of forming transistors and connections thereto'
[patent_app_type] => B2
[patent_app_number] => 09/736547
[patent_app_country] => US
[patent_app_date] => 2000-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 24
[patent_no_of_words] => 4934
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/509/06509213.pdf
[firstpage_image] =>[orig_patent_app_number] => 09736547
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/736547 | Methods of forming transistors and connections thereto | Dec 10, 2000 | Issued |
Array
(
[id] => 1534645
[patent_doc_number] => 06489239
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-03
[patent_title] => 'Method of tungsten chemical vapor deposition and tungsten plug formation'
[patent_app_type] => B1
[patent_app_number] => 09/724151
[patent_app_country] => US
[patent_app_date] => 2000-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3616
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/489/06489239.pdf
[firstpage_image] =>[orig_patent_app_number] => 09724151
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/724151 | Method of tungsten chemical vapor deposition and tungsten plug formation | Nov 27, 2000 | Issued |
Array
(
[id] => 1414431
[patent_doc_number] => 06521508
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-18
[patent_title] => 'Method of manufacturing a contact plug in a semiconductor device using selective epitaxial growth of silicon process'
[patent_app_type] => B1
[patent_app_number] => 09/721938
[patent_app_country] => US
[patent_app_date] => 2000-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2577
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/521/06521508.pdf
[firstpage_image] =>[orig_patent_app_number] => 09721938
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/721938 | Method of manufacturing a contact plug in a semiconductor device using selective epitaxial growth of silicon process | Nov 26, 2000 | Issued |
Array
(
[id] => 4377760
[patent_doc_number] => 06303450
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-16
[patent_title] => 'CMOS device structures and method of making same'
[patent_app_type] => 1
[patent_app_number] => 9/717971
[patent_app_country] => US
[patent_app_date] => 2000-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 8
[patent_no_of_words] => 2185
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/303/06303450.pdf
[firstpage_image] =>[orig_patent_app_number] => 717971
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/717971 | CMOS device structures and method of making same | Nov 20, 2000 | Issued |
Array
(
[id] => 1382530
[patent_doc_number] => 06551931
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-22
[patent_title] => 'Method to selectively cap interconnects with indium or tin bronzes and/or oxides thereof and the interconnect so capped'
[patent_app_type] => B1
[patent_app_number] => 09/706820
[patent_app_country] => US
[patent_app_date] => 2000-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 3262
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/551/06551931.pdf
[firstpage_image] =>[orig_patent_app_number] => 09706820
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/706820 | Method to selectively cap interconnects with indium or tin bronzes and/or oxides thereof and the interconnect so capped | Nov 6, 2000 | Issued |
Array
(
[id] => 4380974
[patent_doc_number] => 06261894
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-17
[patent_title] => 'Method for forming dual workfunction high-performance support MOSFETs in EDRAM arrays'
[patent_app_type] => 1
[patent_app_number] => 9/706492
[patent_app_country] => US
[patent_app_date] => 2000-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 27
[patent_no_of_words] => 6151
[patent_no_of_claims] => 52
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 391
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/261/06261894.pdf
[firstpage_image] =>[orig_patent_app_number] => 706492
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/706492 | Method for forming dual workfunction high-performance support MOSFETs in EDRAM arrays | Nov 2, 2000 | Issued |
Array
(
[id] => 1381173
[patent_doc_number] => 06551849
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-22
[patent_title] => 'Method for fabricating arrays of micro-needles'
[patent_app_type] => B1
[patent_app_number] => 09/705460
[patent_app_country] => US
[patent_app_date] => 2000-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 33
[patent_no_of_words] => 8090
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/551/06551849.pdf
[firstpage_image] =>[orig_patent_app_number] => 09705460
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/705460 | Method for fabricating arrays of micro-needles | Nov 1, 2000 | Issued |
Array
(
[id] => 1570280
[patent_doc_number] => 06498091
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-24
[patent_title] => 'Method of using a barrier sputter reactor to remove an underlying barrier layer'
[patent_app_type] => B1
[patent_app_number] => 09/704161
[patent_app_country] => US
[patent_app_date] => 2000-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 5163
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/498/06498091.pdf
[firstpage_image] =>[orig_patent_app_number] => 09704161
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/704161 | Method of using a barrier sputter reactor to remove an underlying barrier layer | Oct 31, 2000 | Issued |
Array
(
[id] => 4310434
[patent_doc_number] => 06316330
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-13
[patent_title] => 'Method of fabricating a shallow trench isolation semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/699110
[patent_app_country] => US
[patent_app_date] => 2000-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 16
[patent_no_of_words] => 3069
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/316/06316330.pdf
[firstpage_image] =>[orig_patent_app_number] => 699110
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/699110 | Method of fabricating a shallow trench isolation semiconductor device | Oct 25, 2000 | Issued |
Array
(
[id] => 1323965
[patent_doc_number] => 06602734
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-08-05
[patent_title] => 'Method of manufacturing a semiconductor device'
[patent_app_type] => B1
[patent_app_number] => 09/692467
[patent_app_country] => US
[patent_app_date] => 2000-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 25
[patent_no_of_words] => 4263
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/602/06602734.pdf
[firstpage_image] =>[orig_patent_app_number] => 09692467
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/692467 | Method of manufacturing a semiconductor device | Oct 19, 2000 | Issued |
Array
(
[id] => 1462585
[patent_doc_number] => 06350675
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-26
[patent_title] => 'Integration of silicon-rich material in the self-aligned via approach of dual damascene interconnects'
[patent_app_type] => B1
[patent_app_number] => 09/686282
[patent_app_country] => US
[patent_app_date] => 2000-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 7425
[patent_no_of_claims] => 44
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 232
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/350/06350675.pdf
[firstpage_image] =>[orig_patent_app_number] => 09686282
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/686282 | Integration of silicon-rich material in the self-aligned via approach of dual damascene interconnects | Oct 11, 2000 | Issued |
Array
(
[id] => 475588
[patent_doc_number] => 07230877
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-06-12
[patent_title] => 'Method of making a semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 09/685361
[patent_app_country] => US
[patent_app_date] => 2000-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2375
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 226
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/230/07230877.pdf
[firstpage_image] =>[orig_patent_app_number] => 09685361
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/685361 | Method of making a semiconductor memory device | Oct 9, 2000 | Issued |
Array
(
[id] => 1545323
[patent_doc_number] => 06444560
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-03
[patent_title] => 'Process for making fine pitch connections between devices and structure made by the process'
[patent_app_type] => B1
[patent_app_number] => 09/669531
[patent_app_country] => US
[patent_app_date] => 2000-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 19
[patent_no_of_words] => 3986
[patent_no_of_claims] => 44
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/444/06444560.pdf
[firstpage_image] =>[orig_patent_app_number] => 09669531
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/669531 | Process for making fine pitch connections between devices and structure made by the process | Sep 25, 2000 | Issued |
09/646671 | METHOD OF MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE | Sep 19, 2000 | Abandoned |
Array
(
[id] => 4395339
[patent_doc_number] => 06297146
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-02
[patent_title] => 'Low resistivity semiconductor barrier layer manufacturing method'
[patent_app_type] => 1
[patent_app_number] => 9/655108
[patent_app_country] => US
[patent_app_date] => 2000-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2908
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/297/06297146.pdf
[firstpage_image] =>[orig_patent_app_number] => 655108
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/655108 | Low resistivity semiconductor barrier layer manufacturing method | Sep 4, 2000 | Issued |
Array
(
[id] => 1494773
[patent_doc_number] => 06403399
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-11
[patent_title] => 'Method of rapid wafer bumping'
[patent_app_type] => B1
[patent_app_number] => 09/636498
[patent_app_country] => US
[patent_app_date] => 2000-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 3080
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/403/06403399.pdf
[firstpage_image] =>[orig_patent_app_number] => 09636498
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/636498 | Method of rapid wafer bumping | Aug 10, 2000 | Issued |
09/555781 | METHOD FOR MOUNTING EXTERNAL ELECTRODES ON SEMICONDUCTOR ACTUATOR | Aug 9, 2000 | Abandoned |
Array
(
[id] => 4275326
[patent_doc_number] => 06281072
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-28
[patent_title] => 'Multiple step methods for forming conformal layers'
[patent_app_type] => 1
[patent_app_number] => 9/629998
[patent_app_country] => US
[patent_app_date] => 2000-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 7330
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/281/06281072.pdf
[firstpage_image] =>[orig_patent_app_number] => 629998
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/629998 | Multiple step methods for forming conformal layers | Jul 31, 2000 | Issued |