Application number | Title of the application | Filing Date | Status |
---|
Array
(
[id] => 1446631
[patent_doc_number] => 06368954
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-09
[patent_title] => 'Method of copper interconnect formation using atomic layer copper deposition'
[patent_app_type] => B1
[patent_app_number] => 09/627352
[patent_app_country] => US
[patent_app_date] => 2000-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 4076
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/368/06368954.pdf
[firstpage_image] =>[orig_patent_app_number] => 09627352
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/627352 | Method of copper interconnect formation using atomic layer copper deposition | Jul 27, 2000 | Issued |
Array
(
[id] => 4404997
[patent_doc_number] => 06271109
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-07
[patent_title] => 'Substrate for accommodating warped semiconductor devices'
[patent_app_type] => 1
[patent_app_number] => 9/620852
[patent_app_country] => US
[patent_app_date] => 2000-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 12
[patent_no_of_words] => 3490
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 217
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/271/06271109.pdf
[firstpage_image] =>[orig_patent_app_number] => 620852
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/620852 | Substrate for accommodating warped semiconductor devices | Jul 20, 2000 | Issued |
Array
(
[id] => 1490262
[patent_doc_number] => 06417084
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-09
[patent_title] => 'T-gate formation using a modified conventional poly process'
[patent_app_type] => B1
[patent_app_number] => 09/620300
[patent_app_country] => US
[patent_app_date] => 2000-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 3536
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/417/06417084.pdf
[firstpage_image] =>[orig_patent_app_number] => 09620300
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/620300 | T-gate formation using a modified conventional poly process | Jul 19, 2000 | Issued |
Array
(
[id] => 4381898
[patent_doc_number] => 06261955
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-17
[patent_title] => 'Application of vapor phase HFACAC-based compound for use in copper decontamination and cleaning processes'
[patent_app_type] => 1
[patent_app_number] => 9/618262
[patent_app_country] => US
[patent_app_date] => 2000-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 1115
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/261/06261955.pdf
[firstpage_image] =>[orig_patent_app_number] => 618262
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/618262 | Application of vapor phase HFACAC-based compound for use in copper decontamination and cleaning processes | Jul 17, 2000 | Issued |
Array
(
[id] => 1354917
[patent_doc_number] => 06576550
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-06-10
[patent_title] => 'Via first dual damascene process for copper metallization'
[patent_app_type] => B1
[patent_app_number] => 09/608541
[patent_app_country] => US
[patent_app_date] => 2000-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3386
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 344
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/576/06576550.pdf
[firstpage_image] =>[orig_patent_app_number] => 09608541
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/608541 | Via first dual damascene process for copper metallization | Jun 29, 2000 | Issued |
Array
(
[id] => 4377265
[patent_doc_number] => 06303418
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-16
[patent_title] => 'Method of fabricating CMOS devices featuring dual gate structures and a high dielectric constant gate insulator layer'
[patent_app_type] => 1
[patent_app_number] => 9/607282
[patent_app_country] => US
[patent_app_date] => 2000-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 2955
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 491
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/303/06303418.pdf
[firstpage_image] =>[orig_patent_app_number] => 607282
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/607282 | Method of fabricating CMOS devices featuring dual gate structures and a high dielectric constant gate insulator layer | Jun 29, 2000 | Issued |
Array
(
[id] => 1212802
[patent_doc_number] => 06709966
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-03-23
[patent_title] => 'Semiconductor device, its manufacturing process, position matching mark, pattern forming method and pattern forming device'
[patent_app_type] => B1
[patent_app_number] => 09/606152
[patent_app_country] => US
[patent_app_date] => 2000-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 76
[patent_no_of_words] => 14993
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/709/06709966.pdf
[firstpage_image] =>[orig_patent_app_number] => 09606152
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/606152 | Semiconductor device, its manufacturing process, position matching mark, pattern forming method and pattern forming device | Jun 28, 2000 | Issued |
Array
(
[id] => 4336610
[patent_doc_number] => 06333246
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-25
[patent_title] => 'Semiconductor device manufacturing method using electrostatic chuck and semiconductor device manufacturing system'
[patent_app_type] => 1
[patent_app_number] => 9/604722
[patent_app_country] => US
[patent_app_date] => 2000-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 10100
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/333/06333246.pdf
[firstpage_image] =>[orig_patent_app_number] => 604722
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/604722 | Semiconductor device manufacturing method using electrostatic chuck and semiconductor device manufacturing system | Jun 27, 2000 | Issued |
Array
(
[id] => 1549902
[patent_doc_number] => 06346488
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-12
[patent_title] => 'Process to provide enhanced resistance to cracking and to further reduce the dielectric constant of a low dielectric constant dielectric film of an integrated circuit structure by implantation with hydrogen ions'
[patent_app_type] => B1
[patent_app_number] => 09/605382
[patent_app_country] => US
[patent_app_date] => 2000-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2705
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/346/06346488.pdf
[firstpage_image] =>[orig_patent_app_number] => 09605382
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/605382 | Process to provide enhanced resistance to cracking and to further reduce the dielectric constant of a low dielectric constant dielectric film of an integrated circuit structure by implantation with hydrogen ions | Jun 26, 2000 | Issued |
Array
(
[id] => 1433337
[patent_doc_number] => 06340627
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-01-22
[patent_title] => 'Method of making a doped silicon diffusion barrier region'
[patent_app_type] => B1
[patent_app_number] => 09/597064
[patent_app_country] => US
[patent_app_date] => 2000-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 17
[patent_no_of_words] => 2018
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/340/06340627.pdf
[firstpage_image] =>[orig_patent_app_number] => 09597064
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/597064 | Method of making a doped silicon diffusion barrier region | Jun 18, 2000 | Issued |
Array
(
[id] => 1415007
[patent_doc_number] => 06521546
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-18
[patent_title] => 'Method of making a fluoro-organosilicate layer'
[patent_app_type] => B1
[patent_app_number] => 09/593851
[patent_app_country] => US
[patent_app_date] => 2000-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 4719
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/521/06521546.pdf
[firstpage_image] =>[orig_patent_app_number] => 09593851
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/593851 | Method of making a fluoro-organosilicate layer | Jun 13, 2000 | Issued |
Array
(
[id] => 4417506
[patent_doc_number] => 06194310
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-27
[patent_title] => 'Method of forming amorphous conducting diffusion barriers'
[patent_app_type] => 1
[patent_app_number] => 9/585680
[patent_app_country] => US
[patent_app_date] => 2000-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 2829
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/194/06194310.pdf
[firstpage_image] =>[orig_patent_app_number] => 585680
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/585680 | Method of forming amorphous conducting diffusion barriers | May 31, 2000 | Issued |
Array
(
[id] => 4381571
[patent_doc_number] => 06277731
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-21
[patent_title] => 'Method for forming a semiconductor connection with a top surface having an enlarged recess'
[patent_app_type] => 1
[patent_app_number] => 9/584256
[patent_app_country] => US
[patent_app_date] => 2000-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 3512
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/277/06277731.pdf
[firstpage_image] =>[orig_patent_app_number] => 584256
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/584256 | Method for forming a semiconductor connection with a top surface having an enlarged recess | May 30, 2000 | Issued |
Array
(
[id] => 1433341
[patent_doc_number] => 06340631
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-01-22
[patent_title] => 'Method for laying out wide metal lines with embedded contacts/vias'
[patent_app_type] => B1
[patent_app_number] => 09/584112
[patent_app_country] => US
[patent_app_date] => 2000-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 13
[patent_no_of_words] => 3790
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/340/06340631.pdf
[firstpage_image] =>[orig_patent_app_number] => 09584112
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/584112 | Method for laying out wide metal lines with embedded contacts/vias | May 30, 2000 | Issued |
Array
(
[id] => 4395532
[patent_doc_number] => 06297158
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-02
[patent_title] => 'Stress management of barrier metal for resolving CU line corrosion'
[patent_app_type] => 1
[patent_app_number] => 9/583402
[patent_app_country] => US
[patent_app_date] => 2000-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 18
[patent_no_of_words] => 4838
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/297/06297158.pdf
[firstpage_image] =>[orig_patent_app_number] => 583402
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/583402 | Stress management of barrier metal for resolving CU line corrosion | May 30, 2000 | Issued |
Array
(
[id] => 4302360
[patent_doc_number] => 06187621
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-13
[patent_title] => 'Semiconductor processing methods of forming capacitor constructions and semiconductor processing methods of forming DRAM constructions'
[patent_app_type] => 1
[patent_app_number] => 9/580326
[patent_app_country] => US
[patent_app_date] => 2000-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 2268
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/187/06187621.pdf
[firstpage_image] =>[orig_patent_app_number] => 580326
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/580326 | Semiconductor processing methods of forming capacitor constructions and semiconductor processing methods of forming DRAM constructions | May 25, 2000 | Issued |
Array
(
[id] => 1595350
[patent_doc_number] => 06492197
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-10
[patent_title] => 'Trilayer/bilayer solder bumps and fabrication methods therefor'
[patent_app_type] => B1
[patent_app_number] => 09/576477
[patent_app_country] => US
[patent_app_date] => 2000-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 8
[patent_no_of_words] => 5292
[patent_no_of_claims] => 46
[patent_no_of_ind_claims] => 17
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/492/06492197.pdf
[firstpage_image] =>[orig_patent_app_number] => 09576477
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/576477 | Trilayer/bilayer solder bumps and fabrication methods therefor | May 22, 2000 | Issued |
Array
(
[id] => 1421751
[patent_doc_number] => 06509646
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-01-21
[patent_title] => 'Apparatus for reducing an electrical noise inside a ball grid array package'
[patent_app_type] => B1
[patent_app_number] => 09/575637
[patent_app_country] => US
[patent_app_date] => 2000-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 1822
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/509/06509646.pdf
[firstpage_image] =>[orig_patent_app_number] => 09575637
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/575637 | Apparatus for reducing an electrical noise inside a ball grid array package | May 21, 2000 | Issued |
Array
(
[id] => 4354984
[patent_doc_number] => 06200888
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-13
[patent_title] => 'Method of producing semiconductor device comprising insulation layer having improved resistance and semiconductor device produced thereby'
[patent_app_type] => 1
[patent_app_number] => 9/564682
[patent_app_country] => US
[patent_app_date] => 2000-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 26
[patent_no_of_words] => 5860
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/200/06200888.pdf
[firstpage_image] =>[orig_patent_app_number] => 564682
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/564682 | Method of producing semiconductor device comprising insulation layer having improved resistance and semiconductor device produced thereby | May 3, 2000 | Issued |
Array
(
[id] => 4409164
[patent_doc_number] => 06228759
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-08
[patent_title] => 'Method of forming an alloy precipitate to surround interconnect to minimize electromigration'
[patent_app_type] => 1
[patent_app_number] => 9/561622
[patent_app_country] => US
[patent_app_date] => 2000-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 15
[patent_no_of_words] => 4590
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 312
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/228/06228759.pdf
[firstpage_image] =>[orig_patent_app_number] => 561622
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/561622 | Method of forming an alloy precipitate to surround interconnect to minimize electromigration | May 1, 2000 | Issued |