Search

John D Freeman

Examiner (ID: 17393, Phone: (571)270-3469 , Office: P/1787 )

Most Active Art Unit
1787
Art Unit(s)
4174, 1794, 1787
Total Applications
752
Issued Applications
292
Pending Applications
67
Abandoned Applications
393

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4301551 [patent_doc_number] => 06251710 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Method of making a dual damascene anti-fuse with via before wire' [patent_app_type] => 1 [patent_app_number] => 9/560072 [patent_app_country] => US [patent_app_date] => 2000-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3463 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/251/06251710.pdf [firstpage_image] =>[orig_patent_app_number] => 560072 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/560072
Method of making a dual damascene anti-fuse with via before wire Apr 26, 2000 Issued
Array ( [id] => 1379289 [patent_doc_number] => 06555457 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Method of forming a laser circuit having low penetration ohmic contact providing impurity gettering and the resultant laser circuit' [patent_app_type] => B1 [patent_app_number] => 09/545494 [patent_app_country] => US [patent_app_date] => 2000-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5667 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/555/06555457.pdf [firstpage_image] =>[orig_patent_app_number] => 09545494 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/545494
Method of forming a laser circuit having low penetration ohmic contact providing impurity gettering and the resultant laser circuit Apr 6, 2000 Issued
Array ( [id] => 1446578 [patent_doc_number] => 06368926 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Method of forming a semiconductor device with source/drain regions having a deep vertical junction' [patent_app_type] => B1 [patent_app_number] => 09/523632 [patent_app_country] => US [patent_app_date] => 2000-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3004 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/368/06368926.pdf [firstpage_image] =>[orig_patent_app_number] => 09523632 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/523632
Method of forming a semiconductor device with source/drain regions having a deep vertical junction Mar 12, 2000 Issued
Array ( [id] => 4368832 [patent_doc_number] => 06287925 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Formation of highly conductive junctions by rapid thermal anneal and laser thermal process' [patent_app_type] => 1 [patent_app_number] => 9/512202 [patent_app_country] => US [patent_app_date] => 2000-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4057 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287925.pdf [firstpage_image] =>[orig_patent_app_number] => 512202 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/512202
Formation of highly conductive junctions by rapid thermal anneal and laser thermal process Feb 23, 2000 Issued
Array ( [id] => 4326525 [patent_doc_number] => 06319766 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Method of tantalum nitride deposition by tantalum oxide densification' [patent_app_type] => 1 [patent_app_number] => 9/510582 [patent_app_country] => US [patent_app_date] => 2000-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8906 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/319/06319766.pdf [firstpage_image] =>[orig_patent_app_number] => 510582 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/510582
Method of tantalum nitride deposition by tantalum oxide densification Feb 21, 2000 Issued
Array ( [id] => 4294646 [patent_doc_number] => 06184134 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Dry process for cleaning residues/polymers after metal etch' [patent_app_type] => 1 [patent_app_number] => 9/506892 [patent_app_country] => US [patent_app_date] => 2000-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2182 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184134.pdf [firstpage_image] =>[orig_patent_app_number] => 506892 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/506892
Dry process for cleaning residues/polymers after metal etch Feb 17, 2000 Issued
Array ( [id] => 4381233 [patent_doc_number] => 06261911 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Method of manufacturing a junction in a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/502782 [patent_app_country] => US [patent_app_date] => 2000-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 3226 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261911.pdf [firstpage_image] =>[orig_patent_app_number] => 502782 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/502782
Method of manufacturing a junction in a semiconductor device Feb 10, 2000 Issued
Array ( [id] => 1104957 [patent_doc_number] => 06812130 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-02 [patent_title] => 'Self-aligned dual damascene etch using a polymer' [patent_app_type] => B1 [patent_app_number] => 09/501124 [patent_app_country] => US [patent_app_date] => 2000-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3380 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/812/06812130.pdf [firstpage_image] =>[orig_patent_app_number] => 09501124 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/501124
Self-aligned dual damascene etch using a polymer Feb 8, 2000 Issued
Array ( [id] => 4294565 [patent_doc_number] => 06184128 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Method using a thin resist mask for dual damascene stop layer etch' [patent_app_type] => 1 [patent_app_number] => 9/497222 [patent_app_country] => US [patent_app_date] => 2000-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5219 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184128.pdf [firstpage_image] =>[orig_patent_app_number] => 497222 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/497222
Method using a thin resist mask for dual damascene stop layer etch Jan 30, 2000 Issued
Array ( [id] => 1549844 [patent_doc_number] => 06346478 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Method of forming a copper wiring in a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/488521 [patent_app_country] => US [patent_app_date] => 2000-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 8084 [patent_no_of_claims] => 81 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/346/06346478.pdf [firstpage_image] =>[orig_patent_app_number] => 09488521 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/488521
Method of forming a copper wiring in a semiconductor device Jan 20, 2000 Issued
Array ( [id] => 4381173 [patent_doc_number] => 06277705 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Method for fabricating an air-gap with a hard mask' [patent_app_type] => 1 [patent_app_number] => 9/483451 [patent_app_country] => US [patent_app_date] => 2000-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1812 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/277/06277705.pdf [firstpage_image] =>[orig_patent_app_number] => 483451 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/483451
Method for fabricating an air-gap with a hard mask Jan 13, 2000 Issued
Array ( [id] => 7636586 [patent_doc_number] => 06380069 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Method of removing micro-scratch on metal layer' [patent_app_type] => B1 [patent_app_number] => 09/483581 [patent_app_country] => US [patent_app_date] => 2000-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1530 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/380/06380069.pdf [firstpage_image] =>[orig_patent_app_number] => 09483581 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/483581
Method of removing micro-scratch on metal layer Jan 13, 2000 Issued
Array ( [id] => 4381103 [patent_doc_number] => 06277700 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'High selective nitride spacer etch with high ratio of spacer width to deposited nitride thickness' [patent_app_type] => 1 [patent_app_number] => 9/480272 [patent_app_country] => US [patent_app_date] => 2000-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3025 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/277/06277700.pdf [firstpage_image] =>[orig_patent_app_number] => 480272 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/480272
High selective nitride spacer etch with high ratio of spacer width to deposited nitride thickness Jan 10, 2000 Issued
Array ( [id] => 1545371 [patent_doc_number] => 06444567 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Process for alloying damascene-type Cu interconnect lines' [patent_app_type] => B1 [patent_app_number] => 09/477822 [patent_app_country] => US [patent_app_date] => 2000-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6366 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/444/06444567.pdf [firstpage_image] =>[orig_patent_app_number] => 09477822 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/477822
Process for alloying damascene-type Cu interconnect lines Jan 4, 2000 Issued
Array ( [id] => 1440975 [patent_doc_number] => 06335230 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Method for fabricating a simplified CMOS polysilicon thin film transistor and resulting structure' [patent_app_type] => B1 [patent_app_number] => 09/477203 [patent_app_country] => US [patent_app_date] => 2000-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 30 [patent_no_of_words] => 3560 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/335/06335230.pdf [firstpage_image] =>[orig_patent_app_number] => 09477203 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/477203
Method for fabricating a simplified CMOS polysilicon thin film transistor and resulting structure Jan 3, 2000 Issued
Array ( [id] => 4294186 [patent_doc_number] => 06197681 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Forming copper interconnects in dielectric materials with low constant dielectrics' [patent_app_type] => 1 [patent_app_number] => 9/477111 [patent_app_country] => US [patent_app_date] => 1999-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 2550 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/197/06197681.pdf [firstpage_image] =>[orig_patent_app_number] => 477111 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/477111
Forming copper interconnects in dielectric materials with low constant dielectrics Dec 30, 1999 Issued
Array ( [id] => 1565011 [patent_doc_number] => 06339022 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Method of annealing copper metallurgy' [patent_app_type] => B1 [patent_app_number] => 09/475712 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2218 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/339/06339022.pdf [firstpage_image] =>[orig_patent_app_number] => 09475712 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/475712
Method of annealing copper metallurgy Dec 29, 1999 Issued
Array ( [id] => 4275728 [patent_doc_number] => 06281101 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Process of forming metal silicide interconnects' [patent_app_type] => 1 [patent_app_number] => 9/473082 [patent_app_country] => US [patent_app_date] => 1999-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 5354 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281101.pdf [firstpage_image] =>[orig_patent_app_number] => 473082 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/473082
Process of forming metal silicide interconnects Dec 27, 1999 Issued
Array ( [id] => 1495030 [patent_doc_number] => 06403465 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Method to improve copper barrier properties' [patent_app_type] => B1 [patent_app_number] => 09/473033 [patent_app_country] => US [patent_app_date] => 1999-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 3818 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/403/06403465.pdf [firstpage_image] =>[orig_patent_app_number] => 09473033 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/473033
Method to improve copper barrier properties Dec 27, 1999 Issued
Array ( [id] => 1594554 [patent_doc_number] => 06383914 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Method of manufacturing an aluminum interconnect structure of a semiconductor device having <111> orientation' [patent_app_type] => B1 [patent_app_number] => 09/466811 [patent_app_country] => US [patent_app_date] => 1999-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 3284 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/383/06383914.pdf [firstpage_image] =>[orig_patent_app_number] => 09466811 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/466811
Method of manufacturing an aluminum interconnect structure of a semiconductor device having <111> orientation Dec 19, 1999 Issued
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