John D Freeman
Examiner (ID: 17393, Phone: (571)270-3469 , Office: P/1787 )
Most Active Art Unit | 1787 |
Art Unit(s) | 4174, 1794, 1787 |
Total Applications | 752 |
Issued Applications | 292 |
Pending Applications | 67 |
Abandoned Applications | 393 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 4235743
[patent_doc_number] => 06165884
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-26
[patent_title] => 'Method of forming gate electrode in semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/457162
[patent_app_country] => US
[patent_app_date] => 1999-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 1550
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[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/165/06165884.pdf
[firstpage_image] =>[orig_patent_app_number] => 457162
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/457162 | Method of forming gate electrode in semiconductor device | Dec 7, 1999 | Issued |
Array
(
[id] => 4378331
[patent_doc_number] => 06303487
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-16
[patent_title] => 'Method for forming an air gap in an insulating film between adjacent interconnection conductors in a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/454122
[patent_app_country] => US
[patent_app_date] => 1999-12-03
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/303/06303487.pdf
[firstpage_image] =>[orig_patent_app_number] => 454122
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/454122 | Method for forming an air gap in an insulating film between adjacent interconnection conductors in a semiconductor device | Dec 2, 1999 | Issued |
Array
(
[id] => 1433327
[patent_doc_number] => 06340617
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-01-22
[patent_title] => 'Manufacture of semiconductor device'
[patent_app_type] => B1
[patent_app_number] => 09/450507
[patent_app_country] => US
[patent_app_date] => 1999-11-30
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[pdf_file] => patents/06/340/06340617.pdf
[firstpage_image] =>[orig_patent_app_number] => 09450507
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/450507 | Manufacture of semiconductor device | Nov 29, 1999 | Issued |
Array
(
[id] => 4271482
[patent_doc_number] => 06323114
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-27
[patent_title] => 'Stacked/composite gate dielectric which incorporates nitrogen at an interface'
[patent_app_type] => 1
[patent_app_number] => 9/447407
[patent_app_country] => US
[patent_app_date] => 1999-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[pdf_file] => patents/06/323/06323114.pdf
[firstpage_image] =>[orig_patent_app_number] => 447407
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/447407 | Stacked/composite gate dielectric which incorporates nitrogen at an interface | Nov 21, 1999 | Issued |
Array
(
[id] => 1581234
[patent_doc_number] => 06423636
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-23
[patent_title] => 'Process sequence for improved seed layer productivity and achieving 3mm edge exclusion for a copper metalization process on semiconductor wafer'
[patent_app_type] => B1
[patent_app_number] => 09/443832
[patent_app_country] => US
[patent_app_date] => 1999-11-19
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 8091
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[pdf_file] => patents/06/423/06423636.pdf
[firstpage_image] =>[orig_patent_app_number] => 09443832
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/443832 | Process sequence for improved seed layer productivity and achieving 3mm edge exclusion for a copper metalization process on semiconductor wafer | Nov 18, 1999 | Issued |
Array
(
[id] => 4348656
[patent_doc_number] => 06214731
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-10
[patent_title] => 'Copper metalization with improved electromigration resistance'
[patent_app_type] => 1
[patent_app_number] => 9/442771
[patent_app_country] => US
[patent_app_date] => 1999-11-18
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[pdf_file] => patents/06/214/06214731.pdf
[firstpage_image] =>[orig_patent_app_number] => 442771
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/442771 | Copper metalization with improved electromigration resistance | Nov 17, 1999 | Issued |
Array
(
[id] => 1449969
[patent_doc_number] => 06455381
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-24
[patent_title] => 'Method of manufacturing a semiconductor device having a trench isolation structure'
[patent_app_type] => B1
[patent_app_number] => 09/440700
[patent_app_country] => US
[patent_app_date] => 1999-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[pdf_file] => patents/06/455/06455381.pdf
[firstpage_image] =>[orig_patent_app_number] => 09440700
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/440700 | Method of manufacturing a semiconductor device having a trench isolation structure | Nov 15, 1999 | Issued |
Array
(
[id] => 4155693
[patent_doc_number] => 06114243
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-05
[patent_title] => 'Method to avoid copper contamination on the sidewall of a via or a dual damascene structure'
[patent_app_type] => 1
[patent_app_number] => 9/439361
[patent_app_country] => US
[patent_app_date] => 1999-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 2789
[patent_no_of_claims] => 28
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/114/06114243.pdf
[firstpage_image] =>[orig_patent_app_number] => 439361
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/439361 | Method to avoid copper contamination on the sidewall of a via or a dual damascene structure | Nov 14, 1999 | Issued |
Array
(
[id] => 4361067
[patent_doc_number] => 06218735
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-17
[patent_title] => 'Process to improve adhesion of cap layers in intergrated circuits'
[patent_app_type] => 1
[patent_app_number] => 9/439021
[patent_app_country] => US
[patent_app_date] => 1999-11-12
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/218/06218735.pdf
[firstpage_image] =>[orig_patent_app_number] => 439021
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/439021 | Process to improve adhesion of cap layers in intergrated circuits | Nov 11, 1999 | Issued |
Array
(
[id] => 1514545
[patent_doc_number] => 06420258
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-16
[patent_title] => 'Selective growth of copper for advanced metallization'
[patent_app_type] => B1
[patent_app_number] => 09/434564
[patent_app_country] => US
[patent_app_date] => 1999-11-12
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/420/06420258.pdf
[firstpage_image] =>[orig_patent_app_number] => 09434564
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/434564 | Selective growth of copper for advanced metallization | Nov 11, 1999 | Issued |
Array
(
[id] => 4270289
[patent_doc_number] => 06245656
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-12
[patent_title] => 'Method for producing multi-level contacts'
[patent_app_type] => 1
[patent_app_number] => 9/435512
[patent_app_country] => US
[patent_app_date] => 1999-11-08
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[pdf_file] => patents/06/245/06245656.pdf
[firstpage_image] =>[orig_patent_app_number] => 435512
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/435512 | Method for producing multi-level contacts | Nov 7, 1999 | Issued |
Array
(
[id] => 1433345
[patent_doc_number] => 06340635
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-01-22
[patent_title] => 'Resist pattern, process for the formation of the same, and process for the formation of wiring pattern'
[patent_app_type] => B1
[patent_app_number] => 09/433891
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[pdf_file] => patents/06/340/06340635.pdf
[firstpage_image] =>[orig_patent_app_number] => 09433891
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/433891 | Resist pattern, process for the formation of the same, and process for the formation of wiring pattern | Nov 3, 1999 | Issued |
Array
(
[id] => 4380698
[patent_doc_number] => 06261876
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-17
[patent_title] => 'Planar mixed SOI-bulk substrate for microelectronic applications'
[patent_app_type] => 1
[patent_app_number] => 9/434191
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[firstpage_image] =>[orig_patent_app_number] => 434191
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/434191 | Planar mixed SOI-bulk substrate for microelectronic applications | Nov 3, 1999 | Issued |
Array
(
[id] => 1495027
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[patent_title] => 'Method to reduce the moisture content in an organic low dielectric constant material'
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[patent_app_number] => 09/433053
[patent_app_country] => US
[patent_app_date] => 1999-11-03
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/433053 | Method to reduce the moisture content in an organic low dielectric constant material | Nov 2, 1999 | Issued |
Array
(
[id] => 4408500
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[patent_title] => 'Method of forming damascene wiring in a semiconductor device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/433291 | Method of forming damascene wiring in a semiconductor device | Nov 2, 1999 | Issued |
Array
(
[id] => 1458864
[patent_doc_number] => 06426285
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[patent_kind] => B1
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[patent_title] => 'Method to solve intermetallic dielectric cracks in integrated circuit devices'
[patent_app_type] => B1
[patent_app_number] => 09/433054
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Array
(
[id] => 1059536
[patent_doc_number] => 06852626
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-02-08
[patent_title] => 'Film deposition method and apparatus'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/830611 | Film deposition method and apparatus | Oct 28, 1999 | Issued |
Array
(
[id] => 4407622
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/429190 | Method for forming interlayer dielectric layer | Oct 27, 1999 | Issued |
Array
(
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Array
(
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[firstpage_image] =>[orig_patent_app_number] => 427572
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/427572 | Process for forming metal interconnect stack for integrated circuit structure | Oct 25, 1999 | Issued |