Search

John D Freeman

Examiner (ID: 17393, Phone: (571)270-3469 , Office: P/1787 )

Most Active Art Unit
1787
Art Unit(s)
4174, 1794, 1787
Total Applications
752
Issued Applications
292
Pending Applications
67
Abandoned Applications
393

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4095309 [patent_doc_number] => 06096649 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Top metal and passivation procedures for copper damascene structures' [patent_app_type] => 1 [patent_app_number] => 9/425312 [patent_app_country] => US [patent_app_date] => 1999-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 2703 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/096/06096649.pdf [firstpage_image] =>[orig_patent_app_number] => 425312 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/425312
Top metal and passivation procedures for copper damascene structures Oct 24, 1999 Issued
Array ( [id] => 4286893 [patent_doc_number] => 06268266 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Method for forming enhanced FOX region of low voltage device in high voltage process' [patent_app_type] => 1 [patent_app_number] => 9/425600 [patent_app_country] => US [patent_app_date] => 1999-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1956 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268266.pdf [firstpage_image] =>[orig_patent_app_number] => 425600 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/425600
Method for forming enhanced FOX region of low voltage device in high voltage process Oct 21, 1999 Issued
Array ( [id] => 4237467 [patent_doc_number] => 06090696 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Method to improve the adhesion of a molding compound to a semiconductor chip comprised with copper damascene structures' [patent_app_type] => 1 [patent_app_number] => 9/421511 [patent_app_country] => US [patent_app_date] => 1999-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2563 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/090/06090696.pdf [firstpage_image] =>[orig_patent_app_number] => 421511 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/421511
Method to improve the adhesion of a molding compound to a semiconductor chip comprised with copper damascene structures Oct 19, 1999 Issued
Array ( [id] => 6434738 [patent_doc_number] => 20020127809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'METHOD OF FABRICATING A SEMICONDUCTOR DEVICE' [patent_app_type] => new [patent_app_number] => 09/421090 [patent_app_country] => US [patent_app_date] => 1999-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2964 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20020127809.pdf [firstpage_image] =>[orig_patent_app_number] => 09421090 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/421090
Method of fabricating a semiconductor device Oct 18, 1999 Issued
Array ( [id] => 4357935 [patent_doc_number] => 06255149 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Process for restricting interdiffusion in a semiconductor device with composite Si/SiGe gate' [patent_app_type] => 1 [patent_app_number] => 9/403442 [patent_app_country] => US [patent_app_date] => 1999-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 2375 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255149.pdf [firstpage_image] =>[orig_patent_app_number] => 403442 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/403442
Process for restricting interdiffusion in a semiconductor device with composite Si/SiGe gate Oct 18, 1999 Issued
Array ( [id] => 1485348 [patent_doc_number] => 06365504 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Self aligned dual damascene method' [patent_app_type] => B1 [patent_app_number] => 09/418840 [patent_app_country] => US [patent_app_date] => 1999-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2960 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/365/06365504.pdf [firstpage_image] =>[orig_patent_app_number] => 09418840 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/418840
Self aligned dual damascene method Oct 14, 1999 Issued
Array ( [id] => 4102449 [patent_doc_number] => 06100197 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Method of fabricating a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/415922 [patent_app_country] => US [patent_app_date] => 1999-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 3073 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100197.pdf [firstpage_image] =>[orig_patent_app_number] => 415922 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/415922
Method of fabricating a semiconductor device Oct 11, 1999 Issued
Array ( [id] => 4188847 [patent_doc_number] => 06153512 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Process to improve adhesion of HSQ to underlying materials' [patent_app_type] => 1 [patent_app_number] => 9/414922 [patent_app_country] => US [patent_app_date] => 1999-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1961 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/153/06153512.pdf [firstpage_image] =>[orig_patent_app_number] => 414922 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/414922
Process to improve adhesion of HSQ to underlying materials Oct 11, 1999 Issued
Array ( [id] => 4381582 [patent_doc_number] => 06294454 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Method for manufacturing a bed structure underlying electrode pad of semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/414632 [patent_app_country] => US [patent_app_date] => 1999-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 24 [patent_no_of_words] => 5079 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/294/06294454.pdf [firstpage_image] =>[orig_patent_app_number] => 414632 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/414632
Method for manufacturing a bed structure underlying electrode pad of semiconductor device Oct 7, 1999 Issued
Array ( [id] => 4312913 [patent_doc_number] => 06242342 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Fabrication method for a borderless via of a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/414252 [patent_app_country] => US [patent_app_date] => 1999-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2088 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/242/06242342.pdf [firstpage_image] =>[orig_patent_app_number] => 414252 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/414252
Fabrication method for a borderless via of a semiconductor device Oct 6, 1999 Issued
Array ( [id] => 1424432 [patent_doc_number] => 06503820 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Die pad crack absorption system and method for integrated circuit chip fabrication' [patent_app_type] => B1 [patent_app_number] => 09/410942 [patent_app_country] => US [patent_app_date] => 1999-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3201 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/503/06503820.pdf [firstpage_image] =>[orig_patent_app_number] => 09410942 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/410942
Die pad crack absorption system and method for integrated circuit chip fabrication Oct 3, 1999 Issued
Array ( [id] => 4381333 [patent_doc_number] => 06261918 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Method for creating and preserving alignment marks for aligning mask layers in integrated circuit manufacture' [patent_app_type] => 1 [patent_app_number] => 9/411807 [patent_app_country] => US [patent_app_date] => 1999-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 4495 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261918.pdf [firstpage_image] =>[orig_patent_app_number] => 411807 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/411807
Method for creating and preserving alignment marks for aligning mask layers in integrated circuit manufacture Oct 3, 1999 Issued
Array ( [id] => 4358843 [patent_doc_number] => 06255211 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Silicon carbide stop layer in chemical mechanical polishing over metallization layers' [patent_app_type] => 1 [patent_app_number] => 9/410310 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1905 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255211.pdf [firstpage_image] =>[orig_patent_app_number] => 410310 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/410310
Silicon carbide stop layer in chemical mechanical polishing over metallization layers Sep 30, 1999 Issued
Array ( [id] => 4156410 [patent_doc_number] => 06156655 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Retardation layer for preventing diffusion of metal layer and fabrication method thereof' [patent_app_type] => 1 [patent_app_number] => 9/408612 [patent_app_country] => US [patent_app_date] => 1999-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1721 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/156/06156655.pdf [firstpage_image] =>[orig_patent_app_number] => 408612 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/408612
Retardation layer for preventing diffusion of metal layer and fabrication method thereof Sep 29, 1999 Issued
Array ( [id] => 4381603 [patent_doc_number] => 06277733 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Oxygen-free, dry plasma process for polymer removal' [patent_app_type] => 1 [patent_app_number] => 9/408022 [patent_app_country] => US [patent_app_date] => 1999-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2729 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/277/06277733.pdf [firstpage_image] =>[orig_patent_app_number] => 408022 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/408022
Oxygen-free, dry plasma process for polymer removal Sep 28, 1999 Issued
Array ( [id] => 4407481 [patent_doc_number] => 06239008 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Method of making a density multiplier for semiconductor device manufacturing' [patent_app_type] => 1 [patent_app_number] => 9/407907 [patent_app_country] => US [patent_app_date] => 1999-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2745 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/239/06239008.pdf [firstpage_image] =>[orig_patent_app_number] => 407907 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/407907
Method of making a density multiplier for semiconductor device manufacturing Sep 28, 1999 Issued
Array ( [id] => 4269594 [patent_doc_number] => 06245610 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Method of protecting a well at a floating stage' [patent_app_type] => 1 [patent_app_number] => 9/406517 [patent_app_country] => US [patent_app_date] => 1999-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 1836 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/245/06245610.pdf [firstpage_image] =>[orig_patent_app_number] => 406517 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/406517
Method of protecting a well at a floating stage Sep 27, 1999 Issued
Array ( [id] => 4303618 [patent_doc_number] => 06326256 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Method of producing a laser trimmable thin film resistor in an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/406457 [patent_app_country] => US [patent_app_date] => 1999-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3314 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326256.pdf [firstpage_image] =>[orig_patent_app_number] => 406457 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/406457
Method of producing a laser trimmable thin film resistor in an integrated circuit Sep 26, 1999 Issued
Array ( [id] => 4152391 [patent_doc_number] => 06124192 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Method for fabricating ultra-small interconnections using simplified patterns and sidewall contact plugs' [patent_app_type] => 1 [patent_app_number] => 9/405062 [patent_app_country] => US [patent_app_date] => 1999-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2724 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/124/06124192.pdf [firstpage_image] =>[orig_patent_app_number] => 405062 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/405062
Method for fabricating ultra-small interconnections using simplified patterns and sidewall contact plugs Sep 26, 1999 Issued
Array ( [id] => 4407781 [patent_doc_number] => 06239035 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Semiconductor wafer fabrication' [patent_app_type] => 1 [patent_app_number] => 9/404702 [patent_app_country] => US [patent_app_date] => 1999-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 3467 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 403 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/239/06239035.pdf [firstpage_image] =>[orig_patent_app_number] => 404702 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/404702
Semiconductor wafer fabrication Sep 22, 1999 Issued
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