Search

John D Freeman

Examiner (ID: 17393, Phone: (571)270-3469 , Office: P/1787 )

Most Active Art Unit
1787
Art Unit(s)
4174, 1794, 1787
Total Applications
752
Issued Applications
292
Pending Applications
67
Abandoned Applications
393

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7643976 [patent_doc_number] => 06429062 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Integrated-circuit manufacturing using high interstitial-recombination-rate blocking layer for source/drain extension implant' [patent_app_type] => B1 [patent_app_number] => 09/400610 [patent_app_country] => US [patent_app_date] => 1999-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3221 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/429/06429062.pdf [firstpage_image] =>[orig_patent_app_number] => 09400610 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/400610
Integrated-circuit manufacturing using high interstitial-recombination-rate blocking layer for source/drain extension implant Sep 19, 1999 Issued
Array ( [id] => 4219234 [patent_doc_number] => 06040243 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion' [patent_app_type] => 1 [patent_app_number] => 9/398292 [patent_app_country] => US [patent_app_date] => 1999-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2928 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/040/06040243.pdf [firstpage_image] =>[orig_patent_app_number] => 398292 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/398292
Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion Sep 19, 1999 Issued
Array ( [id] => 4102433 [patent_doc_number] => 06100196 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Method of making a copper interconnect with top barrier layer' [patent_app_type] => 1 [patent_app_number] => 9/396254 [patent_app_country] => US [patent_app_date] => 1999-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1845 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100196.pdf [firstpage_image] =>[orig_patent_app_number] => 396254 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/396254
Method of making a copper interconnect with top barrier layer Sep 14, 1999 Issued
Array ( [id] => 4335991 [patent_doc_number] => 06333208 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Robust manufacturing method for making a III-V compound semiconductor device by misaligned wafer bonding' [patent_app_type] => 1 [patent_app_number] => 9/395447 [patent_app_country] => US [patent_app_date] => 1999-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 4287 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/333/06333208.pdf [firstpage_image] =>[orig_patent_app_number] => 395447 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/395447
Robust manufacturing method for making a III-V compound semiconductor device by misaligned wafer bonding Sep 13, 1999 Issued
Array ( [id] => 4420594 [patent_doc_number] => 06225214 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Method for forming contact plug' [patent_app_type] => 1 [patent_app_number] => 9/395111 [patent_app_country] => US [patent_app_date] => 1999-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1993 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225214.pdf [firstpage_image] =>[orig_patent_app_number] => 395111 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/395111
Method for forming contact plug Sep 13, 1999 Issued
Array ( [id] => 4381376 [patent_doc_number] => 06261921 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Method of forming shallow trench isolation structure' [patent_app_type] => 1 [patent_app_number] => 9/395110 [patent_app_country] => US [patent_app_date] => 1999-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2958 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261921.pdf [firstpage_image] =>[orig_patent_app_number] => 395110 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/395110
Method of forming shallow trench isolation structure Sep 13, 1999 Issued
Array ( [id] => 4325184 [patent_doc_number] => 06329276 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Method of forming self-aligned silicide in semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/392470 [patent_app_country] => US [patent_app_date] => 1999-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 3212 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329276.pdf [firstpage_image] =>[orig_patent_app_number] => 392470 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/392470
Method of forming self-aligned silicide in semiconductor device Sep 8, 1999 Issued
Array ( [id] => 4419889 [patent_doc_number] => 06225147 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Methods of forming ICS conductive lines, a conductive grid, a conductive network, an electrical interconnection to a node location, an electrical interconnection with a transistor source/drain region and ICS' [patent_app_type] => 1 [patent_app_number] => 9/392072 [patent_app_country] => US [patent_app_date] => 1999-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 4860 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225147.pdf [firstpage_image] =>[orig_patent_app_number] => 392072 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/392072
Methods of forming ICS conductive lines, a conductive grid, a conductive network, an electrical interconnection to a node location, an electrical interconnection with a transistor source/drain region and ICS Sep 7, 1999 Issued
Array ( [id] => 4382243 [patent_doc_number] => 06261977 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Method for preventing an electrostatic chuck from being corroded during a cleaning process' [patent_app_type] => 1 [patent_app_number] => 9/391357 [patent_app_country] => US [patent_app_date] => 1999-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1630 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261977.pdf [firstpage_image] =>[orig_patent_app_number] => 391357 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/391357
Method for preventing an electrostatic chuck from being corroded during a cleaning process Sep 7, 1999 Issued
Array ( [id] => 4419867 [patent_doc_number] => 06225145 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Method of fabricating vacuum micro-structure' [patent_app_type] => 1 [patent_app_number] => 9/390850 [patent_app_country] => US [patent_app_date] => 1999-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 2056 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225145.pdf [firstpage_image] =>[orig_patent_app_number] => 390850 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/390850
Method of fabricating vacuum micro-structure Sep 6, 1999 Issued
Array ( [id] => 4286540 [patent_doc_number] => 06211057 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Method for manufacturing arch air gap in multilevel interconnection' [patent_app_type] => 1 [patent_app_number] => 9/389887 [patent_app_country] => US [patent_app_date] => 1999-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2689 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/211/06211057.pdf [firstpage_image] =>[orig_patent_app_number] => 389887 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/389887
Method for manufacturing arch air gap in multilevel interconnection Sep 2, 1999 Issued
Array ( [id] => 4395259 [patent_doc_number] => 06297140 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Method to plate C4 to copper stud' [patent_app_type] => 1 [patent_app_number] => 9/389232 [patent_app_country] => US [patent_app_date] => 1999-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3875 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297140.pdf [firstpage_image] =>[orig_patent_app_number] => 389232 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/389232
Method to plate C4 to copper stud Sep 2, 1999 Issued
Array ( [id] => 4408786 [patent_doc_number] => 06300240 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Method for forming bottom anti-reflective coating (BARC)' [patent_app_type] => 1 [patent_app_number] => 9/387730 [patent_app_country] => US [patent_app_date] => 1999-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3248 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/300/06300240.pdf [firstpage_image] =>[orig_patent_app_number] => 387730 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/387730
Method for forming bottom anti-reflective coating (BARC) Aug 31, 1999 Issued
Array ( [id] => 4302991 [patent_doc_number] => 06251806 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Method to improve the roughness of metal deposition on low-k material' [patent_app_type] => 1 [patent_app_number] => 9/373251 [patent_app_country] => US [patent_app_date] => 1999-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4623 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/251/06251806.pdf [firstpage_image] =>[orig_patent_app_number] => 373251 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/373251
Method to improve the roughness of metal deposition on low-k material Aug 11, 1999 Issued
Array ( [id] => 4417572 [patent_doc_number] => 06194316 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Method for forming CU-thin film' [patent_app_type] => 1 [patent_app_number] => 9/368901 [patent_app_country] => US [patent_app_date] => 1999-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3147 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/194/06194316.pdf [firstpage_image] =>[orig_patent_app_number] => 368901 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/368901
Method for forming CU-thin film Aug 5, 1999 Issued
Array ( [id] => 4294496 [patent_doc_number] => 06184123 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Method to prevent delamination of spin-on-glass and plasma nitride layers using ion implantation' [patent_app_type] => 1 [patent_app_number] => 9/365982 [patent_app_country] => US [patent_app_date] => 1999-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2359 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184123.pdf [firstpage_image] =>[orig_patent_app_number] => 365982 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/365982
Method to prevent delamination of spin-on-glass and plasma nitride layers using ion implantation Aug 1, 1999 Issued
Array ( [id] => 7636585 [patent_doc_number] => 06380070 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Semiconductor device having a dual damascene interconnect structure and method for manufacturing same' [patent_app_type] => B1 [patent_app_number] => 09/359873 [patent_app_country] => US [patent_app_date] => 1999-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 2207 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/380/06380070.pdf [firstpage_image] =>[orig_patent_app_number] => 09359873 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/359873
Semiconductor device having a dual damascene interconnect structure and method for manufacturing same Jul 26, 1999 Issued
Array ( [id] => 4381279 [patent_doc_number] => 06261914 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Process for improving local uniformity of chemical mechanical polishing using a self-aligned polish rate enhancement layer' [patent_app_type] => 1 [patent_app_number] => 9/361961 [patent_app_country] => US [patent_app_date] => 1999-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 3716 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261914.pdf [firstpage_image] =>[orig_patent_app_number] => 361961 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/361961
Process for improving local uniformity of chemical mechanical polishing using a self-aligned polish rate enhancement layer Jul 26, 1999 Issued
Array ( [id] => 4191522 [patent_doc_number] => 06130146 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'In-situ nitride and oxynitride deposition process in the same chamber' [patent_app_type] => 1 [patent_app_number] => 9/359893 [patent_app_country] => US [patent_app_date] => 1999-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1934 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/130/06130146.pdf [firstpage_image] =>[orig_patent_app_number] => 359893 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/359893
In-situ nitride and oxynitride deposition process in the same chamber Jul 25, 1999 Issued
09/360102 METHOD OF FABRICATING SEMICONDUCTOR DEVICE Jul 22, 1999 Abandoned
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