John D Freeman
Examiner (ID: 17393, Phone: (571)270-3469 , Office: P/1787 )
Most Active Art Unit | 1787 |
Art Unit(s) | 4174, 1794, 1787 |
Total Applications | 752 |
Issued Applications | 292 |
Pending Applications | 67 |
Abandoned Applications | 393 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 4183577
[patent_doc_number] => 06159837
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-12
[patent_title] => 'Manufacturing method of semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/354271
[patent_app_country] => US
[patent_app_date] => 1999-07-15
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[patent_drawing_sheets_cnt] => 4
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/159/06159837.pdf
[firstpage_image] =>[orig_patent_app_number] => 354271
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/354271 | Manufacturing method of semiconductor device | Jul 14, 1999 | Issued |
Array
(
[id] => 4247132
[patent_doc_number] => 06221734
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[patent_kind] => NA
[patent_issue_date] => 2001-04-24
[patent_title] => 'Method of reducing CMP dishing effect'
[patent_app_type] => 1
[patent_app_number] => 9/354622
[patent_app_country] => US
[patent_app_date] => 1999-07-15
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[pdf_file] => patents/06/221/06221734.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/354622 | Method of reducing CMP dishing effect | Jul 14, 1999 | Issued |
Array
(
[id] => 4302374
[patent_doc_number] => 06251765
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-26
[patent_title] => 'Manufacturing metal dip solder bumps for semiconductor devices'
[patent_app_type] => 1
[patent_app_number] => 9/350041
[patent_app_country] => US
[patent_app_date] => 1999-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/06/251/06251765.pdf
[firstpage_image] =>[orig_patent_app_number] => 350041
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/350041 | Manufacturing metal dip solder bumps for semiconductor devices | Jul 7, 1999 | Issued |
Array
(
[id] => 4325283
[patent_doc_number] => 06329282
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-11
[patent_title] => 'Method of improving the texture of aluminum metallization for tungsten etch back processing'
[patent_app_type] => 1
[patent_app_number] => 9/349624
[patent_app_country] => US
[patent_app_date] => 1999-07-08
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/329/06329282.pdf
[firstpage_image] =>[orig_patent_app_number] => 349624
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/349624 | Method of improving the texture of aluminum metallization for tungsten etch back processing | Jul 7, 1999 | Issued |
Array
(
[id] => 4319149
[patent_doc_number] => 06248665
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-19
[patent_title] => 'Delamination improvement between Cu and dielectrics for damascene process'
[patent_app_type] => 1
[patent_app_number] => 9/347912
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[patent_app_date] => 1999-07-06
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[pdf_file] => patents/06/248/06248665.pdf
[firstpage_image] =>[orig_patent_app_number] => 347912
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/347912 | Delamination improvement between Cu and dielectrics for damascene process | Jul 5, 1999 | Issued |
Array
(
[id] => 4191648
[patent_doc_number] => 06130155
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-10
[patent_title] => 'Method of forming metal lines in an integrated circuit having reduced reaction with an anti-reflection coating'
[patent_app_type] => 1
[patent_app_number] => 9/347171
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[patent_app_date] => 1999-07-02
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[pdf_file] => patents/06/130/06130155.pdf
[firstpage_image] =>[orig_patent_app_number] => 347171
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/347171 | Method of forming metal lines in an integrated circuit having reduced reaction with an anti-reflection coating | Jul 1, 1999 | Issued |
Array
(
[id] => 4310836
[patent_doc_number] => 06316358
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[patent_issue_date] => 2001-11-13
[patent_title] => 'Method for fabricating an integrated circuit device'
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[patent_app_country] => US
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[pdf_file] => patents/06/316/06316358.pdf
[firstpage_image] =>[orig_patent_app_number] => 346271
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/346271 | Method for fabricating an integrated circuit device | Jun 30, 1999 | Issued |
Array
(
[id] => 4405174
[patent_doc_number] => 06271121
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[patent_kind] => NA
[patent_issue_date] => 2001-08-07
[patent_title] => 'Process for chemical vapor deposition of tungsten onto a titanium nitride substrate surface'
[patent_app_type] => 1
[patent_app_number] => 9/345051
[patent_app_country] => US
[patent_app_date] => 1999-06-30
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[pdf_file] => patents/06/271/06271121.pdf
[firstpage_image] =>[orig_patent_app_number] => 345051
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/345051 | Process for chemical vapor deposition of tungsten onto a titanium nitride substrate surface | Jun 29, 1999 | Issued |
Array
(
[id] => 4357478
[patent_doc_number] => 06174802
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[patent_kind] => NA
[patent_issue_date] => 2001-01-16
[patent_title] => 'Method for fabricating a self aligned contact which eliminates the key hole problem using a two step contact deposition'
[patent_app_type] => 1
[patent_app_number] => 9/342042
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/342042 | Method for fabricating a self aligned contact which eliminates the key hole problem using a two step contact deposition | Jun 27, 1999 | Issued |
Array
(
[id] => 4114220
[patent_doc_number] => 06046108
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-04
[patent_title] => 'Method for selective growth of Cu.sub.3 Ge or Cu.sub.5 Si for passivation of damascene copper structures and device manufactured thereby'
[patent_app_type] => 1
[patent_app_number] => 9/344402
[patent_app_country] => US
[patent_app_date] => 1999-06-25
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[pdf_file] => patents/06/046/06046108.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/344402 | Method for selective growth of Cu.sub.3 Ge or Cu.sub.5 Si for passivation of damascene copper structures and device manufactured thereby | Jun 24, 1999 | Issued |
Array
(
[id] => 4188838
[patent_doc_number] => 06153511
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[patent_issue_date] => 2000-11-28
[patent_title] => 'Semiconductor device having a multilayered interconnection structure'
[patent_app_type] => 1
[patent_app_number] => 9/344241
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[patent_app_date] => 1999-06-25
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[firstpage_image] =>[orig_patent_app_number] => 344241
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/344241 | Semiconductor device having a multilayered interconnection structure | Jun 24, 1999 | Issued |
Array
(
[id] => 4214912
[patent_doc_number] => 06110814
[patent_country] => US
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[patent_issue_date] => 2000-08-29
[patent_title] => 'Film forming method and semiconductor device manufacturing method'
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[firstpage_image] =>[orig_patent_app_number] => 330052
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/330052 | Film forming method and semiconductor device manufacturing method | Jun 10, 1999 | Issued |
Array
(
[id] => 4169552
[patent_doc_number] => 06140218
[patent_country] => US
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[patent_issue_date] => 2000-10-31
[patent_title] => 'Method for fabricating a T-shaped hard mask/conductor profile to improve self-aligned contact isolation'
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[patent_app_number] => 9/329782
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Array
(
[id] => 1435909
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[patent_title] => 'Integrated circuit with stop layer and associated fabrication process'
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[patent_app_number] => 09/320201
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/320201 | Integrated circuit with stop layer and associated fabrication process | May 25, 1999 | Issued |
Array
(
[id] => 4286704
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[patent_issue_date] => 2001-04-03
[patent_title] => 'Dual damascene process flow for a deep sub-micron technology'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/312601 | Dual damascene process flow for a deep sub-micron technology | May 16, 1999 | Issued |
Array
(
[id] => 1553431
[patent_doc_number] => 06348366
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[patent_title] => 'Method of forming conductive lines'
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Array
(
[id] => 4408372
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[patent_issue_date] => 2001-10-09
[patent_title] => 'Semiconductor processing methods of forming integrated circuitry, conductive lines, a conductive grid, a conductive network, an electrical interconnection to a node location, and an electrical interconnection with a transistor source/drain region'
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[patent_app_number] => 9/310043
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Array
(
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Array
(
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Array
(
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[firstpage_image] =>[orig_patent_app_number] => 299566
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/299566 | Formation method of interconnection in semiconductor device | Apr 26, 1999 | Issued |