Search

John D Freeman

Examiner (ID: 17393, Phone: (571)270-3469 , Office: P/1787 )

Most Active Art Unit
1787
Art Unit(s)
4174, 1794, 1787
Total Applications
752
Issued Applications
292
Pending Applications
67
Abandoned Applications
393

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4183577 [patent_doc_number] => 06159837 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Manufacturing method of semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/354271 [patent_app_country] => US [patent_app_date] => 1999-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4767 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/159/06159837.pdf [firstpage_image] =>[orig_patent_app_number] => 354271 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/354271
Manufacturing method of semiconductor device Jul 14, 1999 Issued
Array ( [id] => 4247132 [patent_doc_number] => 06221734 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Method of reducing CMP dishing effect' [patent_app_type] => 1 [patent_app_number] => 9/354622 [patent_app_country] => US [patent_app_date] => 1999-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1537 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/221/06221734.pdf [firstpage_image] =>[orig_patent_app_number] => 354622 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/354622
Method of reducing CMP dishing effect Jul 14, 1999 Issued
Array ( [id] => 4302374 [patent_doc_number] => 06251765 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Manufacturing metal dip solder bumps for semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 9/350041 [patent_app_country] => US [patent_app_date] => 1999-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1914 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/251/06251765.pdf [firstpage_image] =>[orig_patent_app_number] => 350041 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/350041
Manufacturing metal dip solder bumps for semiconductor devices Jul 7, 1999 Issued
Array ( [id] => 4325283 [patent_doc_number] => 06329282 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Method of improving the texture of aluminum metallization for tungsten etch back processing' [patent_app_type] => 1 [patent_app_number] => 9/349624 [patent_app_country] => US [patent_app_date] => 1999-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 6 [patent_no_of_words] => 2218 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329282.pdf [firstpage_image] =>[orig_patent_app_number] => 349624 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/349624
Method of improving the texture of aluminum metallization for tungsten etch back processing Jul 7, 1999 Issued
Array ( [id] => 4319149 [patent_doc_number] => 06248665 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Delamination improvement between Cu and dielectrics for damascene process' [patent_app_type] => 1 [patent_app_number] => 9/347912 [patent_app_country] => US [patent_app_date] => 1999-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3799 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/248/06248665.pdf [firstpage_image] =>[orig_patent_app_number] => 347912 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/347912
Delamination improvement between Cu and dielectrics for damascene process Jul 5, 1999 Issued
Array ( [id] => 4191648 [patent_doc_number] => 06130155 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Method of forming metal lines in an integrated circuit having reduced reaction with an anti-reflection coating' [patent_app_type] => 1 [patent_app_number] => 9/347171 [patent_app_country] => US [patent_app_date] => 1999-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 966 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/130/06130155.pdf [firstpage_image] =>[orig_patent_app_number] => 347171 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/347171
Method of forming metal lines in an integrated circuit having reduced reaction with an anti-reflection coating Jul 1, 1999 Issued
Array ( [id] => 4310836 [patent_doc_number] => 06316358 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Method for fabricating an integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 9/346271 [patent_app_country] => US [patent_app_date] => 1999-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2900 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/316/06316358.pdf [firstpage_image] =>[orig_patent_app_number] => 346271 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/346271
Method for fabricating an integrated circuit device Jun 30, 1999 Issued
Array ( [id] => 4405174 [patent_doc_number] => 06271121 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Process for chemical vapor deposition of tungsten onto a titanium nitride substrate surface' [patent_app_type] => 1 [patent_app_number] => 9/345051 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6708 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271121.pdf [firstpage_image] =>[orig_patent_app_number] => 345051 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/345051
Process for chemical vapor deposition of tungsten onto a titanium nitride substrate surface Jun 29, 1999 Issued
Array ( [id] => 4357478 [patent_doc_number] => 06174802 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Method for fabricating a self aligned contact which eliminates the key hole problem using a two step contact deposition' [patent_app_type] => 1 [patent_app_number] => 9/342042 [patent_app_country] => US [patent_app_date] => 1999-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 2479 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/174/06174802.pdf [firstpage_image] =>[orig_patent_app_number] => 342042 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/342042
Method for fabricating a self aligned contact which eliminates the key hole problem using a two step contact deposition Jun 27, 1999 Issued
Array ( [id] => 4114220 [patent_doc_number] => 06046108 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Method for selective growth of Cu.sub.3 Ge or Cu.sub.5 Si for passivation of damascene copper structures and device manufactured thereby' [patent_app_type] => 1 [patent_app_number] => 9/344402 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3437 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/046/06046108.pdf [firstpage_image] =>[orig_patent_app_number] => 344402 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/344402
Method for selective growth of Cu.sub.3 Ge or Cu.sub.5 Si for passivation of damascene copper structures and device manufactured thereby Jun 24, 1999 Issued
Array ( [id] => 4188838 [patent_doc_number] => 06153511 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Semiconductor device having a multilayered interconnection structure' [patent_app_type] => 1 [patent_app_number] => 9/344241 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 28 [patent_no_of_words] => 4525 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/153/06153511.pdf [firstpage_image] =>[orig_patent_app_number] => 344241 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/344241
Semiconductor device having a multilayered interconnection structure Jun 24, 1999 Issued
Array ( [id] => 4214912 [patent_doc_number] => 06110814 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Film forming method and semiconductor device manufacturing method' [patent_app_type] => 1 [patent_app_number] => 9/330052 [patent_app_country] => US [patent_app_date] => 1999-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 8389 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/110/06110814.pdf [firstpage_image] =>[orig_patent_app_number] => 330052 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/330052
Film forming method and semiconductor device manufacturing method Jun 10, 1999 Issued
Array ( [id] => 4169552 [patent_doc_number] => 06140218 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Method for fabricating a T-shaped hard mask/conductor profile to improve self-aligned contact isolation' [patent_app_type] => 1 [patent_app_number] => 9/329782 [patent_app_country] => US [patent_app_date] => 1999-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2237 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/140/06140218.pdf [firstpage_image] =>[orig_patent_app_number] => 329782 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/329782
Method for fabricating a T-shaped hard mask/conductor profile to improve self-aligned contact isolation Jun 9, 1999 Issued
Array ( [id] => 1435909 [patent_doc_number] => 06355552 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Integrated circuit with stop layer and associated fabrication process' [patent_app_type] => B1 [patent_app_number] => 09/320201 [patent_app_country] => US [patent_app_date] => 1999-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 26 [patent_no_of_words] => 3013 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/355/06355552.pdf [firstpage_image] =>[orig_patent_app_number] => 09320201 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/320201
Integrated circuit with stop layer and associated fabrication process May 25, 1999 Issued
Array ( [id] => 4286704 [patent_doc_number] => 06211069 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Dual damascene process flow for a deep sub-micron technology' [patent_app_type] => 1 [patent_app_number] => 9/312601 [patent_app_country] => US [patent_app_date] => 1999-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2007 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 400 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/211/06211069.pdf [firstpage_image] =>[orig_patent_app_number] => 312601 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/312601
Dual damascene process flow for a deep sub-micron technology May 16, 1999 Issued
Array ( [id] => 1553431 [patent_doc_number] => 06348366 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-02-19 [patent_title] => 'Method of forming conductive lines' [patent_app_type] => B2 [patent_app_number] => 09/310037 [patent_app_country] => US [patent_app_date] => 1999-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 4872 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/348/06348366.pdf [firstpage_image] =>[orig_patent_app_number] => 09310037 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/310037
Method of forming conductive lines May 10, 1999 Issued
Array ( [id] => 4408372 [patent_doc_number] => 06300204 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Semiconductor processing methods of forming integrated circuitry, conductive lines, a conductive grid, a conductive network, an electrical interconnection to a node location, and an electrical interconnection with a transistor source/drain region' [patent_app_type] => 1 [patent_app_number] => 9/310043 [patent_app_country] => US [patent_app_date] => 1999-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 4863 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/300/06300204.pdf [firstpage_image] =>[orig_patent_app_number] => 310043 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/310043
Semiconductor processing methods of forming integrated circuitry, conductive lines, a conductive grid, a conductive network, an electrical interconnection to a node location, and an electrical interconnection with a transistor source/drain region May 10, 1999 Issued
Array ( [id] => 1477685 [patent_doc_number] => 06344399 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-05 [patent_title] => 'Method of forming conductive lines and method of forming a conductive grid' [patent_app_type] => B1 [patent_app_number] => 09/310044 [patent_app_country] => US [patent_app_date] => 1999-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 4875 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/344/06344399.pdf [firstpage_image] =>[orig_patent_app_number] => 09310044 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/310044
Method of forming conductive lines and method of forming a conductive grid May 10, 1999 Issued
Array ( [id] => 4215712 [patent_doc_number] => 06087252 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Dual damascene' [patent_app_type] => 1 [patent_app_number] => 9/306092 [patent_app_country] => US [patent_app_date] => 1999-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 1853 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/087/06087252.pdf [firstpage_image] =>[orig_patent_app_number] => 306092 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/306092
Dual damascene May 5, 1999 Issued
Array ( [id] => 4343827 [patent_doc_number] => 06284591 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Formation method of interconnection in semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/299566 [patent_app_country] => US [patent_app_date] => 1999-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 3845 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/284/06284591.pdf [firstpage_image] =>[orig_patent_app_number] => 299566 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/299566
Formation method of interconnection in semiconductor device Apr 26, 1999 Issued
Menu