John D Freeman
Examiner (ID: 17393, Phone: (571)270-3469 , Office: P/1787 )
Most Active Art Unit | 1787 |
Art Unit(s) | 4174, 1794, 1787 |
Total Applications | 752 |
Issued Applications | 292 |
Pending Applications | 67 |
Abandoned Applications | 393 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 4286729
[patent_doc_number] => 06211071
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-03
[patent_title] => 'Optimized trench/via profile for damascene filling'
[patent_app_type] => 1
[patent_app_number] => 9/296552
[patent_app_country] => US
[patent_app_date] => 1999-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 6678
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 376
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/211/06211071.pdf
[firstpage_image] =>[orig_patent_app_number] => 296552
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/296552 | Optimized trench/via profile for damascene filling | Apr 21, 1999 | Issued |
Array
(
[id] => 4417559
[patent_doc_number] => 06194315
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-27
[patent_title] => 'Electrochemical cobalt silicide liner for metal contact fills and damascene processes'
[patent_app_type] => 1
[patent_app_number] => 9/293212
[patent_app_country] => US
[patent_app_date] => 1999-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 3523
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/194/06194315.pdf
[firstpage_image] =>[orig_patent_app_number] => 293212
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/293212 | Electrochemical cobalt silicide liner for metal contact fills and damascene processes | Apr 15, 1999 | Issued |
Array
(
[id] => 4275249
[patent_doc_number] => 06281068
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-28
[patent_title] => 'Method for buried plate formation in deep trench capacitors'
[patent_app_type] => 1
[patent_app_number] => 9/291453
[patent_app_country] => US
[patent_app_date] => 1999-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 4406
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/281/06281068.pdf
[firstpage_image] =>[orig_patent_app_number] => 291453
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/291453 | Method for buried plate formation in deep trench capacitors | Apr 13, 1999 | Issued |
Array
(
[id] => 4291598
[patent_doc_number] => 06180434
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-30
[patent_title] => 'Method for producing a contactless chip card'
[patent_app_type] => 1
[patent_app_number] => 9/284361
[patent_app_country] => US
[patent_app_date] => 1999-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 2088
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/180/06180434.pdf
[firstpage_image] =>[orig_patent_app_number] => 284361
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/284361 | Method for producing a contactless chip card | Apr 12, 1999 | Issued |
Array
(
[id] => 4381722
[patent_doc_number] => 06277741
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-21
[patent_title] => 'Method and planarizing polysilicon layer'
[patent_app_type] => 1
[patent_app_number] => 9/282052
[patent_app_country] => US
[patent_app_date] => 1999-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 1624
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/277/06277741.pdf
[firstpage_image] =>[orig_patent_app_number] => 282052
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/282052 | Method and planarizing polysilicon layer | Mar 28, 1999 | Issued |
Array
(
[id] => 4294157
[patent_doc_number] => 06197679
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-06
[patent_title] => 'Semiconductor device and manufacturing method therefor'
[patent_app_type] => 1
[patent_app_number] => 9/274653
[patent_app_country] => US
[patent_app_date] => 1999-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 25
[patent_no_of_words] => 3948
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/197/06197679.pdf
[firstpage_image] =>[orig_patent_app_number] => 274653
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/274653 | Semiconductor device and manufacturing method therefor | Mar 22, 1999 | Issued |
Array
(
[id] => 4156216
[patent_doc_number] => 06156642
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-05
[patent_title] => 'Method of fabricating a dual damascene structure in an integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 9/274603
[patent_app_country] => US
[patent_app_date] => 1999-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 2877
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/156/06156642.pdf
[firstpage_image] =>[orig_patent_app_number] => 274603
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/274603 | Method of fabricating a dual damascene structure in an integrated circuit | Mar 22, 1999 | Issued |
Array
(
[id] => 4344683
[patent_doc_number] => 06284645
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-04
[patent_title] => 'Controlling improvement of critical dimension of dual damasceue process using spin-on-glass process'
[patent_app_type] => 1
[patent_app_number] => 9/273291
[patent_app_country] => US
[patent_app_date] => 1999-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 16
[patent_no_of_words] => 1798
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/284/06284645.pdf
[firstpage_image] =>[orig_patent_app_number] => 273291
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/273291 | Controlling improvement of critical dimension of dual damasceue process using spin-on-glass process | Mar 18, 1999 | Issued |
Array
(
[id] => 4247688
[patent_doc_number] => 06221773
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-24
[patent_title] => 'Method for working semiconductor wafer'
[patent_app_type] => 1
[patent_app_number] => 9/254431
[patent_app_country] => US
[patent_app_date] => 1999-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 20
[patent_no_of_words] => 4416
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 77
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/221/06221773.pdf
[firstpage_image] =>[orig_patent_app_number] => 254431
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/254431 | Method for working semiconductor wafer | Mar 8, 1999 | Issued |
09/253506 | NANOSTRUCTURE DEVICE AND APPARATUS FOR MAKING | Feb 21, 1999 | Abandoned |
Array
(
[id] => 4417381
[patent_doc_number] => 06194297
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-27
[patent_title] => 'Method for forming salicide layers'
[patent_app_type] => 1
[patent_app_number] => 9/246762
[patent_app_country] => US
[patent_app_date] => 1999-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 1553
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/194/06194297.pdf
[firstpage_image] =>[orig_patent_app_number] => 246762
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/246762 | Method for forming salicide layers | Feb 7, 1999 | Issued |
Array
(
[id] => 4294143
[patent_doc_number] => 06197678
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-06
[patent_title] => 'Damascene process'
[patent_app_type] => 1
[patent_app_number] => 9/241742
[patent_app_country] => US
[patent_app_date] => 1999-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 15
[patent_no_of_words] => 2637
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/197/06197678.pdf
[firstpage_image] =>[orig_patent_app_number] => 241742
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/241742 | Damascene process | Jan 31, 1999 | Issued |
Array
(
[id] => 4289511
[patent_doc_number] => 06235576
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-22
[patent_title] => 'Method for manufacturing a cylindrical capacitor'
[patent_app_type] => 1
[patent_app_number] => 9/241522
[patent_app_country] => US
[patent_app_date] => 1999-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 2207
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/235/06235576.pdf
[firstpage_image] =>[orig_patent_app_number] => 241522
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/241522 | Method for manufacturing a cylindrical capacitor | Jan 31, 1999 | Issued |
Array
(
[id] => 4117087
[patent_doc_number] => 06071805
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-06
[patent_title] => 'Air gap formation for high speed IC processing'
[patent_app_type] => 1
[patent_app_number] => 9/236493
[patent_app_country] => US
[patent_app_date] => 1999-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/071/06071805.pdf
[firstpage_image] =>[orig_patent_app_number] => 236493
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/236493 | Air gap formation for high speed IC processing | Jan 24, 1999 | Issued |
Array
(
[id] => 4247466
[patent_doc_number] => 06221757
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-24
[patent_title] => 'Method of making a microelectronic structure'
[patent_app_type] => 1
[patent_app_number] => 9/234341
[patent_app_country] => US
[patent_app_date] => 1999-01-20
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[patent_drawing_sheets_cnt] => 3
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/221/06221757.pdf
[firstpage_image] =>[orig_patent_app_number] => 234341
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/234341 | Method of making a microelectronic structure | Jan 19, 1999 | Issued |
Array
(
[id] => 4266658
[patent_doc_number] => 06306703
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-23
[patent_title] => 'Memory array having a digit line buried in an isolation region and method for forming same'
[patent_app_type] => 1
[patent_app_number] => 9/234781
[patent_app_country] => US
[patent_app_date] => 1999-01-20
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/306/06306703.pdf
[firstpage_image] =>[orig_patent_app_number] => 234781
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/234781 | Memory array having a digit line buried in an isolation region and method for forming same | Jan 19, 1999 | Issued |
Array
(
[id] => 4357866
[patent_doc_number] => 06191019
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-20
[patent_title] => 'Method for forming a polysilicon layer in a polycide process flow'
[patent_app_type] => 1
[patent_app_number] => 9/229231
[patent_app_country] => US
[patent_app_date] => 1999-01-12
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/191/06191019.pdf
[firstpage_image] =>[orig_patent_app_number] => 229231
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/229231 | Method for forming a polysilicon layer in a polycide process flow | Jan 11, 1999 | Issued |
Array
(
[id] => 4381002
[patent_doc_number] => 06261895
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-17
[patent_title] => 'Polysilicon capacitor having large capacitance and low resistance and process for forming the capacitor'
[patent_app_type] => 1
[patent_app_number] => 9/225043
[patent_app_country] => US
[patent_app_date] => 1999-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/261/06261895.pdf
[firstpage_image] =>[orig_patent_app_number] => 225043
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/225043 | Polysilicon capacitor having large capacitance and low resistance and process for forming the capacitor | Jan 3, 1999 | Issued |
Array
(
[id] => 4130831
[patent_doc_number] => 06146936
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-14
[patent_title] => 'Integrated circuitry, methods of reducing alpha particle inflicted damage to SRAM cells, methods of forming integrated circuitry, and methods of forming SRAM cells'
[patent_app_type] => 1
[patent_app_number] => 9/210257
[patent_app_country] => US
[patent_app_date] => 1998-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/06/146/06146936.pdf
[firstpage_image] =>[orig_patent_app_number] => 210257
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/210257 | Integrated circuitry, methods of reducing alpha particle inflicted damage to SRAM cells, methods of forming integrated circuitry, and methods of forming SRAM cells | Dec 10, 1998 | Issued |
Array
(
[id] => 4131873
[patent_doc_number] => 06121141
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-19
[patent_title] => 'Method of forming a void free copper interconnects'
[patent_app_type] => 1
[patent_app_number] => 9/198362
[patent_app_country] => US
[patent_app_date] => 1998-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/121/06121141.pdf
[firstpage_image] =>[orig_patent_app_number] => 198362
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/198362 | Method of forming a void free copper interconnects | Nov 23, 1998 | Issued |