Search

John D Freeman

Examiner (ID: 17393, Phone: (571)270-3469 , Office: P/1787 )

Most Active Art Unit
1787
Art Unit(s)
4174, 1794, 1787
Total Applications
752
Issued Applications
292
Pending Applications
67
Abandoned Applications
393

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1096039 [patent_doc_number] => 06821872 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-23 [patent_title] => 'Method of making a bit line contact device' [patent_app_type] => B1 [patent_app_number] => 10/709852 [patent_app_country] => US [patent_app_date] => 2004-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 2401 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/821/06821872.pdf [firstpage_image] =>[orig_patent_app_number] => 10709852 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/709852
Method of making a bit line contact device Jun 1, 2004 Issued
Array ( [id] => 662832 [patent_doc_number] => 07101787 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-09-05 [patent_title] => 'System and method for minimizing increases in via resistance by applying a nitrogen plasma after a titanium liner deposition' [patent_app_type] => utility [patent_app_number] => 10/821491 [patent_app_country] => US [patent_app_date] => 2004-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3465 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/101/07101787.pdf [firstpage_image] =>[orig_patent_app_number] => 10821491 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/821491
System and method for minimizing increases in via resistance by applying a nitrogen plasma after a titanium liner deposition Apr 8, 2004 Issued
Array ( [id] => 773516 [patent_doc_number] => 07001836 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-21 [patent_title] => 'Two step trench definition procedure for formation of a dual damascene opening in a stack of insulator layers' [patent_app_type] => utility [patent_app_number] => 10/808802 [patent_app_country] => US [patent_app_date] => 2004-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2124 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/001/07001836.pdf [firstpage_image] =>[orig_patent_app_number] => 10808802 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/808802
Two step trench definition procedure for formation of a dual damascene opening in a stack of insulator layers Mar 24, 2004 Issued
Array ( [id] => 7605431 [patent_doc_number] => 07115498 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-03 [patent_title] => 'Method of ultra-low energy ion implantation to form alloy layers in copper' [patent_app_type] => utility [patent_app_number] => 10/803852 [patent_app_country] => US [patent_app_date] => 2004-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3076 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/115/07115498.pdf [firstpage_image] =>[orig_patent_app_number] => 10803852 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/803852
Method of ultra-low energy ion implantation to form alloy layers in copper Mar 17, 2004 Issued
Array ( [id] => 1107656 [patent_doc_number] => 06808984 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-26 [patent_title] => 'Method for forming a contact opening' [patent_app_type] => B1 [patent_app_number] => 10/802552 [patent_app_country] => US [patent_app_date] => 2004-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2208 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/808/06808984.pdf [firstpage_image] =>[orig_patent_app_number] => 10802552 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/802552
Method for forming a contact opening Mar 16, 2004 Issued
Array ( [id] => 982238 [patent_doc_number] => 06927082 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-09 [patent_title] => 'Method of evaluating the quality of a contact plug fill' [patent_app_type] => utility [patent_app_number] => 10/797672 [patent_app_country] => US [patent_app_date] => 2004-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 819 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/927/06927082.pdf [firstpage_image] =>[orig_patent_app_number] => 10797672 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/797672
Method of evaluating the quality of a contact plug fill Mar 9, 2004 Issued
Array ( [id] => 6944902 [patent_doc_number] => 20050196951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => 'METHOD OF FORMING DUAL DAMASCENE STRUCTURES' [patent_app_type] => utility [patent_app_number] => 10/708502 [patent_app_country] => US [patent_app_date] => 2004-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 5070 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20050196951.pdf [firstpage_image] =>[orig_patent_app_number] => 10708502 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/708502
METHOD OF FORMING DUAL DAMASCENE STRUCTURES Mar 7, 2004 Abandoned
Array ( [id] => 7465792 [patent_doc_number] => 20040166693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'Sputtering target compositions, and methods of inhibiting copper diffusion into a substrate' [patent_app_type] => new [patent_app_number] => 10/783418 [patent_app_country] => US [patent_app_date] => 2004-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6936 [patent_no_of_claims] => 170 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20040166693.pdf [firstpage_image] =>[orig_patent_app_number] => 10783418 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/783418
Sputtering target compositions, and methods of inhibiting copper diffusion into a substrate Feb 18, 2004 Abandoned
Array ( [id] => 1101746 [patent_doc_number] => 06815337 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-09 [patent_title] => 'Method to improve borderless metal line process window for sub-micron designs' [patent_app_type] => B1 [patent_app_number] => 10/781022 [patent_app_country] => US [patent_app_date] => 2004-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2357 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/815/06815337.pdf [firstpage_image] =>[orig_patent_app_number] => 10781022 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/781022
Method to improve borderless metal line process window for sub-micron designs Feb 16, 2004 Issued
Array ( [id] => 645273 [patent_doc_number] => 07119000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-10 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/771391 [patent_app_country] => US [patent_app_date] => 2004-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 3960 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/119/07119000.pdf [firstpage_image] =>[orig_patent_app_number] => 10771391 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/771391
Method of manufacturing semiconductor device Feb 4, 2004 Issued
Array ( [id] => 7039643 [patent_doc_number] => 20050159004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'System for reducing corrosion effects of metallic semiconductor structures' [patent_app_type] => utility [patent_app_number] => 10/760801 [patent_app_country] => US [patent_app_date] => 2004-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3516 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20050159004.pdf [firstpage_image] =>[orig_patent_app_number] => 10760801 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/760801
System for reducing corrosion effects of metallic semiconductor structures Jan 19, 2004 Abandoned
Array ( [id] => 1096066 [patent_doc_number] => 06821882 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-23 [patent_title] => 'Semiconductor device manufacturing method for improving adhesivity of copper metal layer to barrier layer' [patent_app_type] => B2 [patent_app_number] => 10/758392 [patent_app_country] => US [patent_app_date] => 2004-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2738 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/821/06821882.pdf [firstpage_image] =>[orig_patent_app_number] => 10758392 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/758392
Semiconductor device manufacturing method for improving adhesivity of copper metal layer to barrier layer Jan 15, 2004 Issued
Array ( [id] => 7344259 [patent_doc_number] => 20040192033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-30 [patent_title] => 'Semiconductor device, method of manufacturing the same, circuit board, and electronic instrument' [patent_app_type] => new [patent_app_number] => 10/757372 [patent_app_country] => US [patent_app_date] => 2004-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4256 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0192/20040192033.pdf [firstpage_image] =>[orig_patent_app_number] => 10757372 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/757372
Semiconductor device, method of manufacturing the same, circuit board, and electronic instrument Jan 13, 2004 Abandoned
Array ( [id] => 7061291 [patent_doc_number] => 20050003652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'Method and apparatus for low temperature copper to copper bonding' [patent_app_type] => utility [patent_app_number] => 10/746582 [patent_app_country] => US [patent_app_date] => 2003-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4724 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20050003652.pdf [firstpage_image] =>[orig_patent_app_number] => 10746582 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/746582
Method and apparatus for low temperature copper to copper bonding Dec 23, 2003 Abandoned
Array ( [id] => 668436 [patent_doc_number] => 07094677 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-22 [patent_title] => 'Method of forming a penetration electrode and substrate having a penetration electrode' [patent_app_type] => utility [patent_app_number] => 10/736581 [patent_app_country] => US [patent_app_date] => 2003-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2950 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/094/07094677.pdf [firstpage_image] =>[orig_patent_app_number] => 10736581 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/736581
Method of forming a penetration electrode and substrate having a penetration electrode Dec 16, 2003 Issued
Array ( [id] => 686709 [patent_doc_number] => 07078339 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-18 [patent_title] => 'Method of forming metal line layer in semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/731482 [patent_app_country] => US [patent_app_date] => 2003-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 2167 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/078/07078339.pdf [firstpage_image] =>[orig_patent_app_number] => 10731482 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/731482
Method of forming metal line layer in semiconductor device Dec 9, 2003 Issued
Array ( [id] => 1053156 [patent_doc_number] => 06858484 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-22 [patent_title] => 'Method of fabricating semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 10/721902 [patent_app_country] => US [patent_app_date] => 2003-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7048 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 433 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/858/06858484.pdf [firstpage_image] =>[orig_patent_app_number] => 10721902 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/721902
Method of fabricating semiconductor integrated circuit device Nov 25, 2003 Issued
Array ( [id] => 7304997 [patent_doc_number] => 20040115933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-17 [patent_title] => 'Methods of manufacturing a semiconductor device' [patent_app_type] => new [patent_app_number] => 10/722312 [patent_app_country] => US [patent_app_date] => 2003-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2716 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20040115933.pdf [firstpage_image] =>[orig_patent_app_number] => 10722312 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/722312
Methods of manufacturing a semiconductor device Nov 24, 2003 Issued
Array ( [id] => 1071845 [patent_doc_number] => 06841429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-11 [patent_title] => 'Method of manufacturing a semiconductor device having a silicide film' [patent_app_type] => utility [patent_app_number] => 10/716142 [patent_app_country] => US [patent_app_date] => 2003-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 101 [patent_no_of_words] => 9748 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/841/06841429.pdf [firstpage_image] =>[orig_patent_app_number] => 10716142 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/716142
Method of manufacturing a semiconductor device having a silicide film Nov 18, 2003 Issued
Array ( [id] => 7429463 [patent_doc_number] => 20040161932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'SLURRY FOR CMP, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => new [patent_app_number] => 10/706052 [patent_app_country] => US [patent_app_date] => 2003-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8752 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20040161932.pdf [firstpage_image] =>[orig_patent_app_number] => 10706052 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/706052
Slurry for CMP, and method of manufacturing semiconductor device Nov 12, 2003 Issued
Menu