Search

John D Freeman

Examiner (ID: 17393, Phone: (571)270-3469 , Office: P/1787 )

Most Active Art Unit
1787
Art Unit(s)
4174, 1794, 1787
Total Applications
752
Issued Applications
292
Pending Applications
67
Abandoned Applications
393

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7465657 [patent_doc_number] => 20040166669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING DUAL DAMASCENE STRUCTURE' [patent_app_type] => new [patent_app_number] => 10/683392 [patent_app_country] => US [patent_app_date] => 2003-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2794 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20040166669.pdf [firstpage_image] =>[orig_patent_app_number] => 10683392 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/683392
Method of manufacturing semiconductor device having dual damascene structure Oct 13, 2003 Issued
Array ( [id] => 7167196 [patent_doc_number] => 20040077129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Semiconductor chip package with interconnect structure' [patent_app_type] => new [patent_app_number] => 10/685361 [patent_app_country] => US [patent_app_date] => 2003-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8648 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20040077129.pdf [firstpage_image] =>[orig_patent_app_number] => 10685361 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/685361
Semiconductor chip package with interconnect structure Oct 13, 2003 Issued
Array ( [id] => 686606 [patent_doc_number] => 07078300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-18 [patent_title] => 'Thin germanium oxynitride gate dielectric for germanium-based devices' [patent_app_type] => utility [patent_app_number] => 10/672631 [patent_app_country] => US [patent_app_date] => 2003-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2926 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/078/07078300.pdf [firstpage_image] =>[orig_patent_app_number] => 10672631 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/672631
Thin germanium oxynitride gate dielectric for germanium-based devices Sep 26, 2003 Issued
Array ( [id] => 7352983 [patent_doc_number] => 20040048462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-11 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => new [patent_app_number] => 10/648482 [patent_app_country] => US [patent_app_date] => 2003-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5584 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20040048462.pdf [firstpage_image] =>[orig_patent_app_number] => 10648482 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/648482
Method for fabricating semiconductor device Aug 26, 2003 Issued
Array ( [id] => 7395305 [patent_doc_number] => 20040038518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'Methods for forming metal interconnections for semiconductor devices using a buffer layer on a trench sidewall, and semiconductor devices so formed' [patent_app_type] => new [patent_app_number] => 10/644462 [patent_app_country] => US [patent_app_date] => 2003-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4074 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20040038518.pdf [firstpage_image] =>[orig_patent_app_number] => 10644462 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/644462
Methods for forming metal interconnections for semiconductor devices using a buffer layer on a trench sidewall Aug 19, 2003 Issued
Array ( [id] => 1138421 [patent_doc_number] => 06780761 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-24 [patent_title] => 'Via-first dual damascene process' [patent_app_type] => B1 [patent_app_number] => 10/604771 [patent_app_country] => US [patent_app_date] => 2003-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 2870 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/780/06780761.pdf [firstpage_image] =>[orig_patent_app_number] => 10604771 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/604771
Via-first dual damascene process Aug 14, 2003 Issued
Array ( [id] => 7313600 [patent_doc_number] => 20040033650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-19 [patent_title] => 'Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer' [patent_app_type] => new [patent_app_number] => 10/639120 [patent_app_country] => US [patent_app_date] => 2003-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3869 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 577 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20040033650.pdf [firstpage_image] =>[orig_patent_app_number] => 10639120 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/639120
Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer Aug 10, 2003 Issued
Array ( [id] => 1107964 [patent_doc_number] => 06805138 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-19 [patent_title] => 'Semiconductor device production method and semiconductor device production apparatus' [patent_app_type] => B2 [patent_app_number] => 10/637581 [patent_app_country] => US [patent_app_date] => 2003-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 8431 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/805/06805138.pdf [firstpage_image] =>[orig_patent_app_number] => 10637581 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/637581
Semiconductor device production method and semiconductor device production apparatus Aug 10, 2003 Issued
Array ( [id] => 7033855 [patent_doc_number] => 20050032365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-10 [patent_title] => 'Atomic layer deposition of metal during the formation of a semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/637362 [patent_app_country] => US [patent_app_date] => 2003-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3109 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20050032365.pdf [firstpage_image] =>[orig_patent_app_number] => 10637362 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/637362
Atomic layer deposition of metal during the formation of a semiconductor device Aug 7, 2003 Abandoned
Array ( [id] => 1050074 [patent_doc_number] => 06861351 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-01 [patent_title] => 'Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer' [patent_app_type] => utility [patent_app_number] => 10/637102 [patent_app_country] => US [patent_app_date] => 2003-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3879 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/861/06861351.pdf [firstpage_image] =>[orig_patent_app_number] => 10637102 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/637102
Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer Aug 7, 2003 Issued
Array ( [id] => 951288 [patent_doc_number] => 06960490 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-01 [patent_title] => 'Method and resulting structure for manufacturing semiconductor substrates' [patent_app_type] => utility [patent_app_number] => 10/634512 [patent_app_country] => US [patent_app_date] => 2003-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 7691 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/960/06960490.pdf [firstpage_image] =>[orig_patent_app_number] => 10634512 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/634512
Method and resulting structure for manufacturing semiconductor substrates Aug 3, 2003 Issued
Array ( [id] => 1073690 [patent_doc_number] => 06838355 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-04 [patent_title] => 'Damascene interconnect structures including etchback for low-k dielectric materials' [patent_app_type] => utility [patent_app_number] => 10/604602 [patent_app_country] => US [patent_app_date] => 2003-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 25 [patent_no_of_words] => 6977 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/838/06838355.pdf [firstpage_image] =>[orig_patent_app_number] => 10604602 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/604602
Damascene interconnect structures including etchback for low-k dielectric materials Aug 3, 2003 Issued
Array ( [id] => 1126646 [patent_doc_number] => 06790759 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-14 [patent_title] => 'Semiconductor device with strain relieving bump design' [patent_app_type] => B1 [patent_app_number] => 10/631102 [patent_app_country] => US [patent_app_date] => 2003-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 5460 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/790/06790759.pdf [firstpage_image] =>[orig_patent_app_number] => 10631102 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/631102
Semiconductor device with strain relieving bump design Jul 30, 2003 Issued
Array ( [id] => 972706 [patent_doc_number] => 06936925 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-30 [patent_title] => 'Semiconductor device having copper lines with reduced electromigration using an electroplated interim copper-zinc alloy film on a copper surface' [patent_app_type] => utility [patent_app_number] => 10/626371 [patent_app_country] => US [patent_app_date] => 2003-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 6259 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/936/06936925.pdf [firstpage_image] =>[orig_patent_app_number] => 10626371 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/626371
Semiconductor device having copper lines with reduced electromigration using an electroplated interim copper-zinc alloy film on a copper surface Jul 22, 2003 Issued
Array ( [id] => 7677529 [patent_doc_number] => 20040152297 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => new [patent_app_number] => 10/623512 [patent_app_country] => US [patent_app_date] => 2003-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 7863 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20040152297.pdf [firstpage_image] =>[orig_patent_app_number] => 10623512 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/623512
Semiconductor device and manufacturing method thereof Jul 21, 2003 Abandoned
Array ( [id] => 7395368 [patent_doc_number] => 20040038530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'Method for forming a conductive film and a conductive pattern of a semiconductor device' [patent_app_type] => new [patent_app_number] => 10/617721 [patent_app_country] => US [patent_app_date] => 2003-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6669 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20040038530.pdf [firstpage_image] =>[orig_patent_app_number] => 10617721 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/617721
Method for forming a conductive film and a conductive pattern of a semiconductor device Jul 13, 2003 Issued
Array ( [id] => 1037431 [patent_doc_number] => 06872579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-29 [patent_title] => 'Thin-film coil and method of forming same' [patent_app_type] => utility [patent_app_number] => 10/614882 [patent_app_country] => US [patent_app_date] => 2003-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 24 [patent_no_of_words] => 7514 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/872/06872579.pdf [firstpage_image] =>[orig_patent_app_number] => 10614882 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/614882
Thin-film coil and method of forming same Jul 8, 2003 Issued
Array ( [id] => 7471667 [patent_doc_number] => 20040121588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'Method of forming dual damascene pattern in semiconductor device' [patent_app_type] => new [patent_app_number] => 10/614512 [patent_app_country] => US [patent_app_date] => 2003-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2647 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20040121588.pdf [firstpage_image] =>[orig_patent_app_number] => 10614512 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/614512
Method of forming dual damascene pattern in semiconductor device Jul 7, 2003 Issued
Array ( [id] => 7365824 [patent_doc_number] => 20040005786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-08 [patent_title] => 'Method for forming a self-aligned contact hole in a semiconductor device' [patent_app_type] => new [patent_app_number] => 10/608122 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6683 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20040005786.pdf [firstpage_image] =>[orig_patent_app_number] => 10608122 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/608122
Method for forming a self-aligned contact hole in a semiconductor device Jun 29, 2003 Issued
Array ( [id] => 7296550 [patent_doc_number] => 20040214421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'METHOD FOR FORMING CONTACT HOLE OF SEMICONDUCTOR DEVICE' [patent_app_type] => new [patent_app_number] => 10/608116 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2387 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20040214421.pdf [firstpage_image] =>[orig_patent_app_number] => 10608116 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/608116
Method for forming contact hole of semiconductor device Jun 29, 2003 Issued
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