Search

John D Freeman

Examiner (ID: 17393, Phone: (571)270-3469 , Office: P/1787 )

Most Active Art Unit
1787
Art Unit(s)
4174, 1794, 1787
Total Applications
752
Issued Applications
292
Pending Applications
67
Abandoned Applications
393

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7429226 [patent_doc_number] => 20040266070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'METHOD OF FORMING AN INTEGRATED CIRCUIT SUBSTRATE' [patent_app_type] => new [patent_app_number] => 10/612282 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3742 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20040266070.pdf [firstpage_image] =>[orig_patent_app_number] => 10612282 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/612282
Method of forming an integrated circuit substrate Jun 29, 2003 Issued
Array ( [id] => 1134360 [patent_doc_number] => 06784084 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-31 [patent_title] => 'Method for fabricating semiconductor device capable of reducing seam generations' [patent_app_type] => B2 [patent_app_number] => 10/607052 [patent_app_country] => US [patent_app_date] => 2003-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 6368 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/784/06784084.pdf [firstpage_image] =>[orig_patent_app_number] => 10607052 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/607052
Method for fabricating semiconductor device capable of reducing seam generations Jun 26, 2003 Issued
Array ( [id] => 1134414 [patent_doc_number] => 06784093 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-31 [patent_title] => 'Copper surface passivation during semiconductor manufacturing' [patent_app_type] => B1 [patent_app_number] => 10/608921 [patent_app_country] => US [patent_app_date] => 2003-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1961 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/784/06784093.pdf [firstpage_image] =>[orig_patent_app_number] => 10608921 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/608921
Copper surface passivation during semiconductor manufacturing Jun 26, 2003 Issued
Array ( [id] => 1188853 [patent_doc_number] => 06734084 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-11 [patent_title] => 'Method of manufacturing a semiconductor device with recesses using anodic oxide' [patent_app_type] => B1 [patent_app_number] => 10/603982 [patent_app_country] => US [patent_app_date] => 2003-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 11 [patent_no_of_words] => 2629 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/734/06734084.pdf [firstpage_image] =>[orig_patent_app_number] => 10603982 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/603982
Method of manufacturing a semiconductor device with recesses using anodic oxide Jun 25, 2003 Issued
Array ( [id] => 1205483 [patent_doc_number] => 06716691 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-06 [patent_title] => 'Self-aligned shallow trench isolation process having improved polysilicon gate thickness control' [patent_app_type] => B1 [patent_app_number] => 10/606105 [patent_app_country] => US [patent_app_date] => 2003-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 3386 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/716/06716691.pdf [firstpage_image] =>[orig_patent_app_number] => 10606105 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/606105
Self-aligned shallow trench isolation process having improved polysilicon gate thickness control Jun 24, 2003 Issued
Array ( [id] => 1071884 [patent_doc_number] => 06841468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-11 [patent_title] => 'Method of forming a conductive barrier layer having improve adhesion and resistivity characteristics' [patent_app_type] => utility [patent_app_number] => 10/602484 [patent_app_country] => US [patent_app_date] => 2003-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 5619 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/841/06841468.pdf [firstpage_image] =>[orig_patent_app_number] => 10602484 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/602484
Method of forming a conductive barrier layer having improve adhesion and resistivity characteristics Jun 23, 2003 Issued
Array ( [id] => 7328955 [patent_doc_number] => 20040253801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-16 [patent_title] => 'Ultimate low dielectric device and method of making the same' [patent_app_type] => new [patent_app_number] => 10/461236 [patent_app_country] => US [patent_app_date] => 2003-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6258 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20040253801.pdf [firstpage_image] =>[orig_patent_app_number] => 10461236 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/461236
Method of making an ultimate low dielectric device Jun 12, 2003 Issued
Array ( [id] => 646447 [patent_doc_number] => 07119439 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-10 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 10/454667 [patent_app_country] => US [patent_app_date] => 2003-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 49 [patent_no_of_words] => 12641 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/119/07119439.pdf [firstpage_image] =>[orig_patent_app_number] => 10454667 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/454667
Semiconductor device and method for manufacturing the same Jun 4, 2003 Issued
Array ( [id] => 7381725 [patent_doc_number] => 20040081921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Method for manufacturing conductive pattern substrate' [patent_app_type] => new [patent_app_number] => 10/453392 [patent_app_country] => US [patent_app_date] => 2003-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5702 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20040081921.pdf [firstpage_image] =>[orig_patent_app_number] => 10453392 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/453392
Method for manufacturing conductive pattern substrate Jun 2, 2003 Issued
Array ( [id] => 6724835 [patent_doc_number] => 20030207147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-06 [patent_title] => 'Enhancement, stabilization and metallization of porous silicon' [patent_app_type] => new [patent_app_number] => 10/453573 [patent_app_country] => US [patent_app_date] => 2003-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9707 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20030207147.pdf [firstpage_image] =>[orig_patent_app_number] => 10453573 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/453573
Enhancement, stabilization and metallization of porous silicon Jun 2, 2003 Issued
Array ( [id] => 1146649 [patent_doc_number] => 06774032 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-10 [patent_title] => 'Method of making a semiconductor device by forming a masking layer with a tapered etch profile' [patent_app_type] => B1 [patent_app_number] => 10/452681 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 7 [patent_no_of_words] => 2507 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/774/06774032.pdf [firstpage_image] =>[orig_patent_app_number] => 10452681 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/452681
Method of making a semiconductor device by forming a masking layer with a tapered etch profile May 29, 2003 Issued
Array ( [id] => 7620094 [patent_doc_number] => 06943088 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-13 [patent_title] => 'Method of manufacturing a trench isolation structure for a semiconductor device with a different degree of corner rounding' [patent_app_type] => utility [patent_app_number] => 10/444191 [patent_app_country] => US [patent_app_date] => 2003-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 5006 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/943/06943088.pdf [firstpage_image] =>[orig_patent_app_number] => 10444191 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/444191
Method of manufacturing a trench isolation structure for a semiconductor device with a different degree of corner rounding May 22, 2003 Issued
Array ( [id] => 7359796 [patent_doc_number] => 20040014275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => new [patent_app_number] => 10/398034 [patent_app_country] => US [patent_app_date] => 2003-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5176 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 443 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20040014275.pdf [firstpage_image] =>[orig_patent_app_number] => 10398034 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/398034
Method of manufacturing a semiconductor device May 22, 2003 Abandoned
Array ( [id] => 6809183 [patent_doc_number] => 20030199122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => new [patent_app_number] => 10/439110 [patent_app_country] => US [patent_app_date] => 2003-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 4324 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20030199122.pdf [firstpage_image] =>[orig_patent_app_number] => 10439110 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/439110
Method of manufacturing a semiconductor device May 15, 2003 Issued
Array ( [id] => 6770095 [patent_doc_number] => 20030216035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-20 [patent_title] => 'Method and apparatus for sputter deposition' [patent_app_type] => new [patent_app_number] => 10/439021 [patent_app_country] => US [patent_app_date] => 2003-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6432 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20030216035.pdf [firstpage_image] =>[orig_patent_app_number] => 10439021 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/439021
Method and apparatus for sputter deposition May 13, 2003 Abandoned
Array ( [id] => 6723511 [patent_doc_number] => 20030205823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-06 [patent_title] => 'Method for improving nucleation and adhesion of CVD and ALD films deposited onto low-dielectric-constant dielectrics' [patent_app_type] => new [patent_app_number] => 10/435704 [patent_app_country] => US [patent_app_date] => 2003-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6124 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20030205823.pdf [firstpage_image] =>[orig_patent_app_number] => 10435704 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/435704
Method for improving nucleation and adhesion of CVD and ALD films deposited onto low-dielectric-constant dielectrics May 8, 2003 Abandoned
Array ( [id] => 7204112 [patent_doc_number] => 20040087145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-06 [patent_title] => 'Semiconductor device and method of manufacturing' [patent_app_type] => new [patent_app_number] => 10/311628 [patent_app_country] => US [patent_app_date] => 2003-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1136 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20040087145.pdf [firstpage_image] =>[orig_patent_app_number] => 10311628 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/311628
Semiconductor device and method of manufacturing May 4, 2003 Abandoned
Array ( [id] => 6725256 [patent_doc_number] => 20030207568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-06 [patent_title] => 'Organometallic precursor for forming metal pattern and method of forming metal pattern using the same' [patent_app_type] => new [patent_app_number] => 10/425882 [patent_app_country] => US [patent_app_date] => 2003-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 7282 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20030207568.pdf [firstpage_image] =>[orig_patent_app_number] => 10425882 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/425882
Organometallic precursor for forming metal pattern and method of forming metal pattern using the same Apr 29, 2003 Issued
Array ( [id] => 6663800 [patent_doc_number] => 20030203126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-30 [patent_title] => 'Organometal complex and method of depositing a metal silicate thin layer using same' [patent_app_type] => new [patent_app_number] => 10/423337 [patent_app_country] => US [patent_app_date] => 2003-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2343 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 7 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20030203126.pdf [firstpage_image] =>[orig_patent_app_number] => 10423337 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/423337
Organometal complex and method of depositing a metal silicate thin layer using same Apr 24, 2003 Issued
Array ( [id] => 1155858 [patent_doc_number] => 06764940 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-20 [patent_title] => 'Method for depositing a diffusion barrier for copper interconnect applications' [patent_app_type] => B1 [patent_app_number] => 10/412562 [patent_app_country] => US [patent_app_date] => 2003-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 8743 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/764/06764940.pdf [firstpage_image] =>[orig_patent_app_number] => 10412562 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/412562
Method for depositing a diffusion barrier for copper interconnect applications Apr 10, 2003 Issued
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