Search

John D Freeman

Examiner (ID: 17393, Phone: (571)270-3469 , Office: P/1787 )

Most Active Art Unit
1787
Art Unit(s)
4174, 1794, 1787
Total Applications
752
Issued Applications
292
Pending Applications
67
Abandoned Applications
393

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1065621 [patent_doc_number] => 06846747 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-25 [patent_title] => 'Method for etching vias' [patent_app_type] => utility [patent_app_number] => 10/407831 [patent_app_country] => US [patent_app_date] => 2003-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3490 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/846/06846747.pdf [firstpage_image] =>[orig_patent_app_number] => 10407831 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/407831
Method for etching vias Apr 3, 2003 Issued
Array ( [id] => 6874563 [patent_doc_number] => 20030194860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-16 [patent_title] => 'Semiconductor device manufacturing method and electronic equipment using same' [patent_app_type] => new [patent_app_number] => 10/405462 [patent_app_country] => US [patent_app_date] => 2003-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 18572 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20030194860.pdf [firstpage_image] =>[orig_patent_app_number] => 10405462 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/405462
Semiconductor device manufacturing method and electronic equipment using same Apr 2, 2003 Issued
Array ( [id] => 6729790 [patent_doc_number] => 20030185980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-02 [patent_title] => 'Thin film forming method and a semiconductor device manufacturing method' [patent_app_type] => new [patent_app_number] => 10/401970 [patent_app_country] => US [patent_app_date] => 2003-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10164 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20030185980.pdf [firstpage_image] =>[orig_patent_app_number] => 10401970 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/401970
Thin film forming method and a semiconductor device manufacturing method Mar 30, 2003 Abandoned
Array ( [id] => 6905725 [patent_doc_number] => 20050101120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-12 [patent_title] => 'Method of forming local interconnect barrier layers' [patent_app_type] => utility [patent_app_number] => 10/400212 [patent_app_country] => US [patent_app_date] => 2003-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4103 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20050101120.pdf [firstpage_image] =>[orig_patent_app_number] => 10400212 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/400212
Method of forming local interconnect barrier layers Mar 26, 2003 Abandoned
Array ( [id] => 1149537 [patent_doc_number] => 06770554 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-03 [patent_title] => 'On-chip interconnect circuits with use of large-sized copper fill in CMP process' [patent_app_type] => B1 [patent_app_number] => 10/402692 [patent_app_country] => US [patent_app_date] => 2003-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2295 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/770/06770554.pdf [firstpage_image] =>[orig_patent_app_number] => 10402692 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/402692
On-chip interconnect circuits with use of large-sized copper fill in CMP process Mar 26, 2003 Issued
Array ( [id] => 6664298 [patent_doc_number] => 20030203624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-30 [patent_title] => 'Manufacturing method of semiconductor device' [patent_app_type] => new [patent_app_number] => 10/394051 [patent_app_country] => US [patent_app_date] => 2003-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 18105 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20030203624.pdf [firstpage_image] =>[orig_patent_app_number] => 10394051 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/394051
Manufacturing method of semiconductor device Mar 23, 2003 Abandoned
Array ( [id] => 7443037 [patent_doc_number] => 20040185656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-23 [patent_title] => 'FILLING SMALL DIMENSION VIAS USING SUPERCRITICAL CARBON DIOXIDE' [patent_app_type] => new [patent_app_number] => 10/393712 [patent_app_country] => US [patent_app_date] => 2003-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1629 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20040185656.pdf [firstpage_image] =>[orig_patent_app_number] => 10393712 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/393712
Filling small dimension vias using supercritical carbon dioxide Mar 20, 2003 Issued
Array ( [id] => 1126666 [patent_doc_number] => 06790766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-14 [patent_title] => 'Method of fabricating semiconductor device having low dielectric constant insulator film' [patent_app_type] => B2 [patent_app_number] => 10/391022 [patent_app_country] => US [patent_app_date] => 2003-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 7442 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/790/06790766.pdf [firstpage_image] =>[orig_patent_app_number] => 10391022 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/391022
Method of fabricating semiconductor device having low dielectric constant insulator film Mar 18, 2003 Issued
Array ( [id] => 1126589 [patent_doc_number] => 06790737 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-14 [patent_title] => 'Method for fabricating thin metal layers from the liquid phase' [patent_app_type] => B2 [patent_app_number] => 10/390872 [patent_app_country] => US [patent_app_date] => 2003-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 6612 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/790/06790737.pdf [firstpage_image] =>[orig_patent_app_number] => 10390872 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/390872
Method for fabricating thin metal layers from the liquid phase Mar 16, 2003 Issued
Array ( [id] => 1264522 [patent_doc_number] => 06660628 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-09 [patent_title] => 'Method of MOCVD Ti-based barrier metal thin films with tetrakis (methylethylamino) titanium with octane' [patent_app_type] => B1 [patent_app_number] => 10/391291 [patent_app_country] => US [patent_app_date] => 2003-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1454 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/660/06660628.pdf [firstpage_image] =>[orig_patent_app_number] => 10391291 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/391291
Method of MOCVD Ti-based barrier metal thin films with tetrakis (methylethylamino) titanium with octane Mar 16, 2003 Issued
Array ( [id] => 1146616 [patent_doc_number] => 06774027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-10 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => B2 [patent_app_number] => 10/385931 [patent_app_country] => US [patent_app_date] => 2003-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 42 [patent_no_of_words] => 6120 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/774/06774027.pdf [firstpage_image] =>[orig_patent_app_number] => 10385931 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/385931
Semiconductor device and method for manufacturing the same Mar 10, 2003 Issued
Array ( [id] => 1106069 [patent_doc_number] => 06812486 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-02 [patent_title] => 'Conductive structure and method of forming the structure' [patent_app_type] => B1 [patent_app_number] => 10/371431 [patent_app_country] => US [patent_app_date] => 2003-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 40 [patent_no_of_words] => 8929 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/812/06812486.pdf [firstpage_image] =>[orig_patent_app_number] => 10371431 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/371431
Conductive structure and method of forming the structure Feb 19, 2003 Issued
Array ( [id] => 1178780 [patent_doc_number] => 06747358 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-08 [patent_title] => 'Self-aligned alloy capping layers for copper interconnect structures' [patent_app_type] => B1 [patent_app_number] => 10/368760 [patent_app_country] => US [patent_app_date] => 2003-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 5929 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/747/06747358.pdf [firstpage_image] =>[orig_patent_app_number] => 10368760 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/368760
Self-aligned alloy capping layers for copper interconnect structures Feb 17, 2003 Issued
Array ( [id] => 7465522 [patent_doc_number] => 20040053498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-18 [patent_title] => 'Method and apparatus for forming damascene structure, and damascene structure' [patent_app_type] => new [patent_app_number] => 10/365642 [patent_app_country] => US [patent_app_date] => 2003-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8991 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20040053498.pdf [firstpage_image] =>[orig_patent_app_number] => 10365642 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/365642
Method and apparatus for forming damascene structure, and damascene structure Feb 12, 2003 Abandoned
Array ( [id] => 1104952 [patent_doc_number] => 06812128 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-02 [patent_title] => 'Method of manufacturing multilayer structured semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/364341 [patent_app_country] => US [patent_app_date] => 2003-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 20 [patent_no_of_words] => 3245 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/812/06812128.pdf [firstpage_image] =>[orig_patent_app_number] => 10364341 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/364341
Method of manufacturing multilayer structured semiconductor device Feb 11, 2003 Issued
Array ( [id] => 6740411 [patent_doc_number] => 20030157780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-21 [patent_title] => 'Method of alignment for buried structures formed by surface transformation of empty spaces in solid state materials' [patent_app_type] => new [patent_app_number] => 10/360925 [patent_app_country] => US [patent_app_date] => 2003-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6668 [patent_no_of_claims] => 103 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20030157780.pdf [firstpage_image] =>[orig_patent_app_number] => 10360925 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/360925
Method of alignment for buried structures formed by surface transformation of empty spaces in solid state materials Feb 9, 2003 Issued
Array ( [id] => 7135224 [patent_doc_number] => 20040043611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Method of reducing a defect level after chemically mechanically polishing a copper-containing substrate by rinsing the substrate with an oxidizing solution' [patent_app_type] => new [patent_app_number] => 10/360221 [patent_app_country] => US [patent_app_date] => 2003-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3721 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20040043611.pdf [firstpage_image] =>[orig_patent_app_number] => 10360221 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/360221
Method of reducing a defect level after chemically mechanically polishing a copper-containing substrate by rinsing the substrate with an oxidizing solution Feb 5, 2003 Abandoned
Array ( [id] => 1068734 [patent_doc_number] => 06844260 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-18 [patent_title] => 'Insitu post atomic layer deposition destruction of active species' [patent_app_type] => utility [patent_app_number] => 10/356981 [patent_app_country] => US [patent_app_date] => 2003-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 4820 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/844/06844260.pdf [firstpage_image] =>[orig_patent_app_number] => 10356981 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/356981
Insitu post atomic layer deposition destruction of active species Jan 29, 2003 Issued
Array ( [id] => 7287326 [patent_doc_number] => 20040147116 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-29 [patent_title] => 'Novel method to reduce stress for copper CMP' [patent_app_type] => new [patent_app_number] => 10/353421 [patent_app_country] => US [patent_app_date] => 2003-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3926 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20040147116.pdf [firstpage_image] =>[orig_patent_app_number] => 10353421 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/353421
Novel method to reduce stress for copper CMP Jan 28, 2003 Abandoned
Array ( [id] => 7287315 [patent_doc_number] => 20040147110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-29 [patent_title] => 'Method of forming integrated circuit contacts' [patent_app_type] => new [patent_app_number] => 10/350691 [patent_app_country] => US [patent_app_date] => 2003-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4113 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20040147110.pdf [firstpage_image] =>[orig_patent_app_number] => 10350691 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/350691
Method of forming integrated circuit contacts Jan 23, 2003 Issued
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