John D Freeman
Examiner (ID: 17393, Phone: (571)270-3469 , Office: P/1787 )
Most Active Art Unit | 1787 |
Art Unit(s) | 4174, 1794, 1787 |
Total Applications | 752 |
Issued Applications | 292 |
Pending Applications | 67 |
Abandoned Applications | 393 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 1065621
[patent_doc_number] => 06846747
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-01-25
[patent_title] => 'Method for etching vias'
[patent_app_type] => utility
[patent_app_number] => 10/407831
[patent_app_country] => US
[patent_app_date] => 2003-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 3490
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/846/06846747.pdf
[firstpage_image] =>[orig_patent_app_number] => 10407831
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/407831 | Method for etching vias | Apr 3, 2003 | Issued |
Array
(
[id] => 6874563
[patent_doc_number] => 20030194860
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-16
[patent_title] => 'Semiconductor device manufacturing method and electronic equipment using same'
[patent_app_type] => new
[patent_app_number] => 10/405462
[patent_app_country] => US
[patent_app_date] => 2003-04-03
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[pdf_file] => publications/A1/0194/20030194860.pdf
[firstpage_image] =>[orig_patent_app_number] => 10405462
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/405462 | Semiconductor device manufacturing method and electronic equipment using same | Apr 2, 2003 | Issued |
Array
(
[id] => 6729790
[patent_doc_number] => 20030185980
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[patent_kind] => A1
[patent_issue_date] => 2003-10-02
[patent_title] => 'Thin film forming method and a semiconductor device manufacturing method'
[patent_app_type] => new
[patent_app_number] => 10/401970
[patent_app_country] => US
[patent_app_date] => 2003-03-31
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[pdf_file] => publications/A1/0185/20030185980.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/401970 | Thin film forming method and a semiconductor device manufacturing method | Mar 30, 2003 | Abandoned |
Array
(
[id] => 6905725
[patent_doc_number] => 20050101120
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-12
[patent_title] => 'Method of forming local interconnect barrier layers'
[patent_app_type] => utility
[patent_app_number] => 10/400212
[patent_app_country] => US
[patent_app_date] => 2003-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => publications/A1/0101/20050101120.pdf
[firstpage_image] =>[orig_patent_app_number] => 10400212
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/400212 | Method of forming local interconnect barrier layers | Mar 26, 2003 | Abandoned |
Array
(
[id] => 1149537
[patent_doc_number] => 06770554
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-08-03
[patent_title] => 'On-chip interconnect circuits with use of large-sized copper fill in CMP process'
[patent_app_type] => B1
[patent_app_number] => 10/402692
[patent_app_country] => US
[patent_app_date] => 2003-03-27
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/770/06770554.pdf
[firstpage_image] =>[orig_patent_app_number] => 10402692
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/402692 | On-chip interconnect circuits with use of large-sized copper fill in CMP process | Mar 26, 2003 | Issued |
Array
(
[id] => 6664298
[patent_doc_number] => 20030203624
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-30
[patent_title] => 'Manufacturing method of semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/394051
[patent_app_country] => US
[patent_app_date] => 2003-03-24
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[pdf_file] => publications/A1/0203/20030203624.pdf
[firstpage_image] =>[orig_patent_app_number] => 10394051
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/394051 | Manufacturing method of semiconductor device | Mar 23, 2003 | Abandoned |
Array
(
[id] => 7443037
[patent_doc_number] => 20040185656
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[patent_kind] => A1
[patent_issue_date] => 2004-09-23
[patent_title] => 'FILLING SMALL DIMENSION VIAS USING SUPERCRITICAL CARBON DIOXIDE'
[patent_app_type] => new
[patent_app_number] => 10/393712
[patent_app_country] => US
[patent_app_date] => 2003-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 1629
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[pdf_file] => publications/A1/0185/20040185656.pdf
[firstpage_image] =>[orig_patent_app_number] => 10393712
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/393712 | Filling small dimension vias using supercritical carbon dioxide | Mar 20, 2003 | Issued |
Array
(
[id] => 1126666
[patent_doc_number] => 06790766
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-09-14
[patent_title] => 'Method of fabricating semiconductor device having low dielectric constant insulator film'
[patent_app_type] => B2
[patent_app_number] => 10/391022
[patent_app_country] => US
[patent_app_date] => 2003-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[pdf_file] => patents/06/790/06790766.pdf
[firstpage_image] =>[orig_patent_app_number] => 10391022
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/391022 | Method of fabricating semiconductor device having low dielectric constant insulator film | Mar 18, 2003 | Issued |
Array
(
[id] => 1126589
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[patent_issue_date] => 2004-09-14
[patent_title] => 'Method for fabricating thin metal layers from the liquid phase'
[patent_app_type] => B2
[patent_app_number] => 10/390872
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[patent_app_date] => 2003-03-17
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[pdf_file] => patents/06/790/06790737.pdf
[firstpage_image] =>[orig_patent_app_number] => 10390872
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/390872 | Method for fabricating thin metal layers from the liquid phase | Mar 16, 2003 | Issued |
Array
(
[id] => 1264522
[patent_doc_number] => 06660628
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-12-09
[patent_title] => 'Method of MOCVD Ti-based barrier metal thin films with tetrakis (methylethylamino) titanium with octane'
[patent_app_type] => B1
[patent_app_number] => 10/391291
[patent_app_country] => US
[patent_app_date] => 2003-03-17
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/660/06660628.pdf
[firstpage_image] =>[orig_patent_app_number] => 10391291
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/391291 | Method of MOCVD Ti-based barrier metal thin films with tetrakis (methylethylamino) titanium with octane | Mar 16, 2003 | Issued |
Array
(
[id] => 1146616
[patent_doc_number] => 06774027
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-10
[patent_title] => 'Semiconductor device and method for manufacturing the same'
[patent_app_type] => B2
[patent_app_number] => 10/385931
[patent_app_country] => US
[patent_app_date] => 2003-03-11
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[pdf_file] => patents/06/774/06774027.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/385931 | Semiconductor device and method for manufacturing the same | Mar 10, 2003 | Issued |
Array
(
[id] => 1106069
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[patent_issue_date] => 2004-11-02
[patent_title] => 'Conductive structure and method of forming the structure'
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[firstpage_image] =>[orig_patent_app_number] => 10371431
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/371431 | Conductive structure and method of forming the structure | Feb 19, 2003 | Issued |
Array
(
[id] => 1178780
[patent_doc_number] => 06747358
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[patent_issue_date] => 2004-06-08
[patent_title] => 'Self-aligned alloy capping layers for copper interconnect structures'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/368760 | Self-aligned alloy capping layers for copper interconnect structures | Feb 17, 2003 | Issued |
Array
(
[id] => 7465522
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[patent_title] => 'Method and apparatus for forming damascene structure, and damascene structure'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/365642 | Method and apparatus for forming damascene structure, and damascene structure | Feb 12, 2003 | Abandoned |
Array
(
[id] => 1104952
[patent_doc_number] => 06812128
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[patent_issue_date] => 2004-11-02
[patent_title] => 'Method of manufacturing multilayer structured semiconductor device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/364341 | Method of manufacturing multilayer structured semiconductor device | Feb 11, 2003 | Issued |
Array
(
[id] => 6740411
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[patent_title] => 'Method of alignment for buried structures formed by surface transformation of empty spaces in solid state materials'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/360925 | Method of alignment for buried structures formed by surface transformation of empty spaces in solid state materials | Feb 9, 2003 | Issued |
Array
(
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[patent_title] => 'Method of reducing a defect level after chemically mechanically polishing a copper-containing substrate by rinsing the substrate with an oxidizing solution'
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[patent_app_number] => 10/360221
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Array
(
[id] => 1068734
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[patent_title] => 'Insitu post atomic layer deposition destruction of active species'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/356981 | Insitu post atomic layer deposition destruction of active species | Jan 29, 2003 | Issued |
Array
(
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[patent_title] => 'Novel method to reduce stress for copper CMP'
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Array
(
[id] => 7287315
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[patent_title] => 'Method of forming integrated circuit contacts'
[patent_app_type] => new
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[firstpage_image] =>[orig_patent_app_number] => 10350691
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/350691 | Method of forming integrated circuit contacts | Jan 23, 2003 | Issued |