Search

John D Freeman

Examiner (ID: 17393, Phone: (571)270-3469 , Office: P/1787 )

Most Active Art Unit
1787
Art Unit(s)
4174, 1794, 1787
Total Applications
752
Issued Applications
292
Pending Applications
67
Abandoned Applications
393

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1177497 [patent_doc_number] => 06743719 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-01 [patent_title] => 'Method for forming a conductive copper structure' [patent_app_type] => B1 [patent_app_number] => 10/348821 [patent_app_country] => US [patent_app_date] => 2003-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3114 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/743/06743719.pdf [firstpage_image] =>[orig_patent_app_number] => 10348821 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/348821
Method for forming a conductive copper structure Jan 21, 2003 Issued
Array ( [id] => 6847172 [patent_doc_number] => 20030166339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-04 [patent_title] => 'CMP system for metal deposition' [patent_app_type] => new [patent_app_number] => 10/347831 [patent_app_country] => US [patent_app_date] => 2003-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9506 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20030166339.pdf [firstpage_image] =>[orig_patent_app_number] => 10347831 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/347831
CMP system for metal deposition Jan 20, 2003 Issued
Array ( [id] => 1134398 [patent_doc_number] => 06784088 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-31 [patent_title] => 'Method to selectively cap interconnects with indium or tin bronzes and/or oxides thereof and the interconnect so capped' [patent_app_type] => B2 [patent_app_number] => 10/345288 [patent_app_country] => US [patent_app_date] => 2003-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 3290 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/784/06784088.pdf [firstpage_image] =>[orig_patent_app_number] => 10345288 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/345288
Method to selectively cap interconnects with indium or tin bronzes and/or oxides thereof and the interconnect so capped Jan 15, 2003 Issued
Array ( [id] => 935419 [patent_doc_number] => 06974768 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-13 [patent_title] => 'Methods of providing an adhesion layer for adhesion of barrier and/or seed layers to dielectric films' [patent_app_type] => utility [patent_app_number] => 10/342522 [patent_app_country] => US [patent_app_date] => 2003-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5301 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/974/06974768.pdf [firstpage_image] =>[orig_patent_app_number] => 10342522 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/342522
Methods of providing an adhesion layer for adhesion of barrier and/or seed layers to dielectric films Jan 14, 2003 Issued
Array ( [id] => 1306756 [patent_doc_number] => 06617241 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-09 [patent_title] => 'Method of thick film planarization' [patent_app_type] => B1 [patent_app_number] => 10/345761 [patent_app_country] => US [patent_app_date] => 2003-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 1758 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/617/06617241.pdf [firstpage_image] =>[orig_patent_app_number] => 10345761 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/345761
Method of thick film planarization Jan 14, 2003 Issued
Array ( [id] => 1112816 [patent_doc_number] => 06803241 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-12 [patent_title] => 'Method of monitoring contact hole of integrated circuit using corona charges' [patent_app_type] => B2 [patent_app_number] => 10/338832 [patent_app_country] => US [patent_app_date] => 2003-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4255 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/803/06803241.pdf [firstpage_image] =>[orig_patent_app_number] => 10338832 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/338832
Method of monitoring contact hole of integrated circuit using corona charges Jan 8, 2003 Issued
Array ( [id] => 6856320 [patent_doc_number] => 20030129821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-10 [patent_title] => ' BUMP FABRICATION METHOD\n ' [patent_app_type] => new-utility [patent_app_number] => 10/248292 [patent_app_country] => US [patent_app_date] => 2003-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2300 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20030129821.pdf [firstpage_image] =>[orig_patent_app_number] => 10248292 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/248292
Bump fabrication method Jan 5, 2003 Issued
Array ( [id] => 1111055 [patent_doc_number] => 06806189 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-19 [patent_title] => 'Method of silver (AG) electroless plating on ITO electrode' [patent_app_type] => B2 [patent_app_number] => 10/330431 [patent_app_country] => US [patent_app_date] => 2002-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3799 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/806/06806189.pdf [firstpage_image] =>[orig_patent_app_number] => 10330431 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/330431
Method of silver (AG) electroless plating on ITO electrode Dec 29, 2002 Issued
Array ( [id] => 7465511 [patent_doc_number] => 20040053496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-18 [patent_title] => 'Method for forming metal films' [patent_app_type] => new [patent_app_number] => 10/329522 [patent_app_country] => US [patent_app_date] => 2002-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3328 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20040053496.pdf [firstpage_image] =>[orig_patent_app_number] => 10329522 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/329522
Method for forming metal films Dec 26, 2002 Issued
Array ( [id] => 1163423 [patent_doc_number] => 06759322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-06 [patent_title] => 'Method for forming wiring structure' [patent_app_type] => B2 [patent_app_number] => 10/328171 [patent_app_country] => US [patent_app_date] => 2002-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 8121 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/759/06759322.pdf [firstpage_image] =>[orig_patent_app_number] => 10328171 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/328171
Method for forming wiring structure Dec 25, 2002 Issued
Array ( [id] => 1040578 [patent_doc_number] => 06869876 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-22 [patent_title] => 'Process for atomic layer deposition of metal films' [patent_app_type] => utility [patent_app_number] => 10/324781 [patent_app_country] => US [patent_app_date] => 2002-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 7589 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/869/06869876.pdf [firstpage_image] =>[orig_patent_app_number] => 10324781 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/324781
Process for atomic layer deposition of metal films Dec 19, 2002 Issued
Array ( [id] => 6790129 [patent_doc_number] => 20030085473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-08 [patent_title] => 'Semiconductor device and manufacturing method thereof for realizing high packaging density' [patent_app_type] => new [patent_app_number] => 10/322651 [patent_app_country] => US [patent_app_date] => 2002-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4278 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20030085473.pdf [firstpage_image] =>[orig_patent_app_number] => 10322651 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/322651
Semiconductor device and manufacturing method thereof for realizing high packaging density Dec 18, 2002 Abandoned
Array ( [id] => 7471493 [patent_doc_number] => 20040121550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'Method for creating barriers to metal contamination in silicon oxides' [patent_app_type] => new [patent_app_number] => 10/325373 [patent_app_country] => US [patent_app_date] => 2002-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1592 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20040121550.pdf [firstpage_image] =>[orig_patent_app_number] => 10325373 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/325373
Method for creating barriers to metal contamination in silicon oxides Dec 18, 2002 Abandoned
Array ( [id] => 6683430 [patent_doc_number] => 20030119294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'METHOD FOR FORMING WIRING IN SEMICONDUCTOR DEVICE' [patent_app_type] => new [patent_app_number] => 10/323021 [patent_app_country] => US [patent_app_date] => 2002-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1748 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20030119294.pdf [firstpage_image] =>[orig_patent_app_number] => 10323021 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/323021
Method for forming wiring in semiconductor device Dec 17, 2002 Issued
Array ( [id] => 6761479 [patent_doc_number] => 20030124841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-03 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => new [patent_app_number] => 10/318101 [patent_app_country] => US [patent_app_date] => 2002-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4150 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20030124841.pdf [firstpage_image] =>[orig_patent_app_number] => 10318101 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/318101
Method for fabricating semiconductor device Dec 12, 2002 Abandoned
Array ( [id] => 6854245 [patent_doc_number] => 20030127746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-10 [patent_title] => 'Panel stacking of BGA devices to form three-dimensional modules' [patent_app_type] => new [patent_app_number] => 10/316566 [patent_app_country] => US [patent_app_date] => 2002-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10023 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20030127746.pdf [firstpage_image] =>[orig_patent_app_number] => 10316566 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/316566
Panel stacking of BGA devices to form three-dimensional modules Dec 10, 2002 Issued
Array ( [id] => 1112954 [patent_doc_number] => 06803300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-12 [patent_title] => 'Method of manufacturing a semiconductor device having a ground plane' [patent_app_type] => B2 [patent_app_number] => 10/314995 [patent_app_country] => US [patent_app_date] => 2002-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 22 [patent_no_of_words] => 3942 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/803/06803300.pdf [firstpage_image] =>[orig_patent_app_number] => 10314995 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/314995
Method of manufacturing a semiconductor device having a ground plane Dec 9, 2002 Issued
Array ( [id] => 1291158 [patent_doc_number] => 06630397 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-07 [patent_title] => 'Method to improve surface uniformity of a layer of arc used for the creation of contact plugs' [patent_app_type] => B1 [patent_app_number] => 10/315532 [patent_app_country] => US [patent_app_date] => 2002-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5409 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/630/06630397.pdf [firstpage_image] =>[orig_patent_app_number] => 10315532 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/315532
Method to improve surface uniformity of a layer of arc used for the creation of contact plugs Dec 9, 2002 Issued
Array ( [id] => 7273101 [patent_doc_number] => 20040232552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Air gap dual damascene process and structure' [patent_app_type] => new [patent_app_number] => 10/314151 [patent_app_country] => US [patent_app_date] => 2002-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3863 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20040232552.pdf [firstpage_image] =>[orig_patent_app_number] => 10314151 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/314151
Air gap dual damascene process and structure Dec 8, 2002 Abandoned
Array ( [id] => 1181062 [patent_doc_number] => 06737349 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-18 [patent_title] => 'Method of forming a copper wiring in a semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/310722 [patent_app_country] => US [patent_app_date] => 2002-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1916 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/737/06737349.pdf [firstpage_image] =>[orig_patent_app_number] => 10310722 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/310722
Method of forming a copper wiring in a semiconductor device Dec 4, 2002 Issued
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