John D Freeman
Examiner (ID: 17393, Phone: (571)270-3469 , Office: P/1787 )
Most Active Art Unit | 1787 |
Art Unit(s) | 4174, 1794, 1787 |
Total Applications | 752 |
Issued Applications | 292 |
Pending Applications | 67 |
Abandoned Applications | 393 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 1177497
[patent_doc_number] => 06743719
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-06-01
[patent_title] => 'Method for forming a conductive copper structure'
[patent_app_type] => B1
[patent_app_number] => 10/348821
[patent_app_country] => US
[patent_app_date] => 2003-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_words_short_claim] => 86
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/743/06743719.pdf
[firstpage_image] =>[orig_patent_app_number] => 10348821
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/348821 | Method for forming a conductive copper structure | Jan 21, 2003 | Issued |
Array
(
[id] => 6847172
[patent_doc_number] => 20030166339
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-09-04
[patent_title] => 'CMP system for metal deposition'
[patent_app_type] => new
[patent_app_number] => 10/347831
[patent_app_country] => US
[patent_app_date] => 2003-01-21
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0166/20030166339.pdf
[firstpage_image] =>[orig_patent_app_number] => 10347831
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/347831 | CMP system for metal deposition | Jan 20, 2003 | Issued |
Array
(
[id] => 1134398
[patent_doc_number] => 06784088
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-31
[patent_title] => 'Method to selectively cap interconnects with indium or tin bronzes and/or oxides thereof and the interconnect so capped'
[patent_app_type] => B2
[patent_app_number] => 10/345288
[patent_app_country] => US
[patent_app_date] => 2003-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[pdf_file] => patents/06/784/06784088.pdf
[firstpage_image] =>[orig_patent_app_number] => 10345288
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/345288 | Method to selectively cap interconnects with indium or tin bronzes and/or oxides thereof and the interconnect so capped | Jan 15, 2003 | Issued |
Array
(
[id] => 935419
[patent_doc_number] => 06974768
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-12-13
[patent_title] => 'Methods of providing an adhesion layer for adhesion of barrier and/or seed layers to dielectric films'
[patent_app_type] => utility
[patent_app_number] => 10/342522
[patent_app_country] => US
[patent_app_date] => 2003-01-15
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 10342522
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/342522 | Methods of providing an adhesion layer for adhesion of barrier and/or seed layers to dielectric films | Jan 14, 2003 | Issued |
Array
(
[id] => 1306756
[patent_doc_number] => 06617241
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-09-09
[patent_title] => 'Method of thick film planarization'
[patent_app_type] => B1
[patent_app_number] => 10/345761
[patent_app_country] => US
[patent_app_date] => 2003-01-15
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[pdf_file] => patents/06/617/06617241.pdf
[firstpage_image] =>[orig_patent_app_number] => 10345761
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/345761 | Method of thick film planarization | Jan 14, 2003 | Issued |
Array
(
[id] => 1112816
[patent_doc_number] => 06803241
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-10-12
[patent_title] => 'Method of monitoring contact hole of integrated circuit using corona charges'
[patent_app_type] => B2
[patent_app_number] => 10/338832
[patent_app_country] => US
[patent_app_date] => 2003-01-09
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[firstpage_image] =>[orig_patent_app_number] => 10338832
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/338832 | Method of monitoring contact hole of integrated circuit using corona charges | Jan 8, 2003 | Issued |
Array
(
[id] => 6856320
[patent_doc_number] => 20030129821
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-07-10
[patent_title] => ' BUMP FABRICATION METHOD\n '
[patent_app_type] => new-utility
[patent_app_number] => 10/248292
[patent_app_country] => US
[patent_app_date] => 2003-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[firstpage_image] =>[orig_patent_app_number] => 10248292
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/248292 | Bump fabrication method | Jan 5, 2003 | Issued |
Array
(
[id] => 1111055
[patent_doc_number] => 06806189
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-10-19
[patent_title] => 'Method of silver (AG) electroless plating on ITO electrode'
[patent_app_type] => B2
[patent_app_number] => 10/330431
[patent_app_country] => US
[patent_app_date] => 2002-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 3799
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[pdf_file] => patents/06/806/06806189.pdf
[firstpage_image] =>[orig_patent_app_number] => 10330431
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/330431 | Method of silver (AG) electroless plating on ITO electrode | Dec 29, 2002 | Issued |
Array
(
[id] => 7465511
[patent_doc_number] => 20040053496
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-18
[patent_title] => 'Method for forming metal films'
[patent_app_type] => new
[patent_app_number] => 10/329522
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[firstpage_image] =>[orig_patent_app_number] => 10329522
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/329522 | Method for forming metal films | Dec 26, 2002 | Issued |
Array
(
[id] => 1163423
[patent_doc_number] => 06759322
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-07-06
[patent_title] => 'Method for forming wiring structure'
[patent_app_type] => B2
[patent_app_number] => 10/328171
[patent_app_country] => US
[patent_app_date] => 2002-12-26
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/759/06759322.pdf
[firstpage_image] =>[orig_patent_app_number] => 10328171
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/328171 | Method for forming wiring structure | Dec 25, 2002 | Issued |
Array
(
[id] => 1040578
[patent_doc_number] => 06869876
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-03-22
[patent_title] => 'Process for atomic layer deposition of metal films'
[patent_app_type] => utility
[patent_app_number] => 10/324781
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[patent_app_date] => 2002-12-20
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[pdf_file] => patents/06/869/06869876.pdf
[firstpage_image] =>[orig_patent_app_number] => 10324781
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/324781 | Process for atomic layer deposition of metal films | Dec 19, 2002 | Issued |
Array
(
[id] => 6790129
[patent_doc_number] => 20030085473
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-05-08
[patent_title] => 'Semiconductor device and manufacturing method thereof for realizing high packaging density'
[patent_app_type] => new
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/322651 | Semiconductor device and manufacturing method thereof for realizing high packaging density | Dec 18, 2002 | Abandoned |
Array
(
[id] => 7471493
[patent_doc_number] => 20040121550
[patent_country] => US
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[patent_issue_date] => 2004-06-24
[patent_title] => 'Method for creating barriers to metal contamination in silicon oxides'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/325373 | Method for creating barriers to metal contamination in silicon oxides | Dec 18, 2002 | Abandoned |
Array
(
[id] => 6683430
[patent_doc_number] => 20030119294
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-26
[patent_title] => 'METHOD FOR FORMING WIRING IN SEMICONDUCTOR DEVICE'
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[patent_app_number] => 10/323021
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[firstpage_image] =>[orig_patent_app_number] => 10323021
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/323021 | Method for forming wiring in semiconductor device | Dec 17, 2002 | Issued |
Array
(
[id] => 6761479
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[patent_title] => 'Method for fabricating semiconductor device'
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[pdf_file] => publications/A1/0124/20030124841.pdf
[firstpage_image] =>[orig_patent_app_number] => 10318101
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/318101 | Method for fabricating semiconductor device | Dec 12, 2002 | Abandoned |
Array
(
[id] => 6854245
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[patent_issue_date] => 2003-07-10
[patent_title] => 'Panel stacking of BGA devices to form three-dimensional modules'
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[firstpage_image] =>[orig_patent_app_number] => 10316566
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/316566 | Panel stacking of BGA devices to form three-dimensional modules | Dec 10, 2002 | Issued |
Array
(
[id] => 1112954
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[patent_title] => 'Method of manufacturing a semiconductor device having a ground plane'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/314995 | Method of manufacturing a semiconductor device having a ground plane | Dec 9, 2002 | Issued |
Array
(
[id] => 1291158
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[patent_title] => 'Method to improve surface uniformity of a layer of arc used for the creation of contact plugs'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/315532 | Method to improve surface uniformity of a layer of arc used for the creation of contact plugs | Dec 9, 2002 | Issued |
Array
(
[id] => 7273101
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[patent_issue_date] => 2004-11-25
[patent_title] => 'Air gap dual damascene process and structure'
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[firstpage_image] =>[orig_patent_app_number] => 10314151
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/314151 | Air gap dual damascene process and structure | Dec 8, 2002 | Abandoned |
Array
(
[id] => 1181062
[patent_doc_number] => 06737349
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[patent_title] => 'Method of forming a copper wiring in a semiconductor device'
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[pdf_file] => patents/06/737/06737349.pdf
[firstpage_image] =>[orig_patent_app_number] => 10310722
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/310722 | Method of forming a copper wiring in a semiconductor device | Dec 4, 2002 | Issued |