John D. Lee

Array ( [id] => 5285017 [patent_doc_number] => 20090098692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-16 [patent_title] => 'Method for Fabricating a Semiconductor Gate Structure' [patent_app_type] => utility [patent_app_number] => 11/872298 [patent_app_country] => US [patent_app_date] => 2007-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3640 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20090098692.pdf [firstpage_image] =>[orig_patent_app_number] => 11872298 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4965384 [patent_doc_number] => 20080108204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'AMORPHIZATION/TEMPLATED RECRYSTALLIZATION METHOD FOR HYBRID ORIENTATION SUBSTRATES' [patent_app_type] => utility [patent_app_number] => 11/871694 [patent_app_country] => US [patent_app_date] => 2007-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6140 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20080108204.pdf [firstpage_image] =>[orig_patent_app_number] => 11871694 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4532111 [patent_doc_number] => 07923758 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-04-12 [patent_title] => 'Method and apparatus for producing gallium arsenide and silicon composites and devices incorporating same' [patent_app_type] => utility [patent_app_number] => 11/973680 [patent_app_country] => US [patent_app_date] => 2007-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 30 [patent_no_of_words] => 9399 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/923/07923758.pdf [firstpage_image] =>[orig_patent_app_number] => 11973680 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4657702 [patent_doc_number] => 20080026563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'SEMICONDUCTOR DEVICE MANUFACTURING DEVICE' [patent_app_type] => utility [patent_app_number] => 11/863403 [patent_app_country] => US [patent_app_date] => 2007-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9863 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20080026563.pdf [firstpage_image] =>[orig_patent_app_number] => 11863403 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5428646 [patent_doc_number] => 20090087956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'Dummy Contact Fill to Improve Post Contact Chemical Mechanical Polish Topography' [patent_app_type] => utility [patent_app_number] => 11/862668 [patent_app_country] => US [patent_app_date] => 2007-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2707 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20090087956.pdf [firstpage_image] =>[orig_patent_app_number] => 11862668 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4483665 [patent_doc_number] => 07902018 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-08 [patent_title] => 'Fluorine plasma treatment of high-k gate stack for defect passivation' [patent_app_type] => utility [patent_app_number] => 11/861578 [patent_app_country] => US [patent_app_date] => 2007-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6577 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/902/07902018.pdf [firstpage_image] =>[orig_patent_app_number] => 11861578 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7490564 [patent_doc_number] => 08030212 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-04 [patent_title] => 'Process for selective area deposition of inorganic materials' [patent_app_type] => utility [patent_app_number] => 11/861658 [patent_app_country] => US [patent_app_date] => 2007-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 16440 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/030/08030212.pdf [firstpage_image] =>[orig_patent_app_number] => 11861658 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9388981 [patent_doc_number] => 08685576 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-04-01 [patent_title] => 'Electrically conductive porous membrane' [patent_app_type] => utility [patent_app_number] => 11/860661 [patent_app_country] => US [patent_app_date] => 2007-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 6472 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11860661 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4745751 [patent_doc_number] => 20080090353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'Method of Manufacturing Non-Volatile Memory Device' [patent_app_type] => utility [patent_app_number] => 11/859618 [patent_app_country] => US [patent_app_date] => 2007-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5327 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20080090353.pdf [firstpage_image] =>[orig_patent_app_number] => 11859618 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5508657 [patent_doc_number] => 20090081864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'SiC Film for Semiconductor Processing' [patent_app_type] => utility [patent_app_number] => 11/859119 [patent_app_country] => US [patent_app_date] => 2007-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3888 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20090081864.pdf [firstpage_image] =>[orig_patent_app_number] => 11859119 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4474704 [patent_doc_number] => 07867878 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-11 [patent_title] => 'Stacked semiconductor chips' [patent_app_type] => utility [patent_app_number] => 11/859329 [patent_app_country] => US [patent_app_date] => 2007-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 22 [patent_no_of_words] => 4830 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/867/07867878.pdf [firstpage_image] =>[orig_patent_app_number] => 11859329 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4963079 [patent_doc_number] => 20080105899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'SEMICONDUCTOR DEVICE WITH EPITAXIALLY GROWN LAYER AND FABRICATION METHOD' [patent_app_type] => utility [patent_app_number] => 11/858288 [patent_app_country] => US [patent_app_date] => 2007-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4682 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20080105899.pdf [firstpage_image] =>[orig_patent_app_number] => 11858288 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4941800 [patent_doc_number] => 20080079123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-03 [patent_title] => 'METHOD OF FABRICATING A MIXED MICROTECHNOLOGY STRUCTUE AND A STRUCTURE OBTAINED THEREBY' [patent_app_type] => utility [patent_app_number] => 11/857130 [patent_app_country] => US [patent_app_date] => 2007-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7414 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20080079123.pdf [firstpage_image] =>[orig_patent_app_number] => 11857130 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4919341 [patent_doc_number] => 20080067653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'Reduction in Thickness of Semiconductor Component on Substrate' [patent_app_type] => utility [patent_app_number] => 11/856769 [patent_app_country] => US [patent_app_date] => 2007-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3228 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20080067653.pdf [firstpage_image] =>[orig_patent_app_number] => 11856769 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5268625 [patent_doc_number] => 20090072400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-19 [patent_title] => 'CONTACT FORMING IN TWO PORTIONS AND CONTACT SO FORMED' [patent_app_type] => utility [patent_app_number] => 11/856839 [patent_app_country] => US [patent_app_date] => 2007-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 2510 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20090072400.pdf [firstpage_image] =>[orig_patent_app_number] => 11856839 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4715189 [patent_doc_number] => 20080237711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'MANUFACTURING METHOD OF THIN-FILM SEMICONDUCTOR APPARATUS AND THIN-FILM SEMICONDUCTOR APPARATUS' [patent_app_type] => utility [patent_app_number] => 11/857050 [patent_app_country] => US [patent_app_date] => 2007-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3802 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20080237711.pdf [firstpage_image] =>[orig_patent_app_number] => 11857050 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4574101 [patent_doc_number] => 07825031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Method of fabricating a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/855809 [patent_app_country] => US [patent_app_date] => 2007-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 54 [patent_no_of_words] => 7067 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/825/07825031.pdf [firstpage_image] =>[orig_patent_app_number] => 11855809 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4483786 [patent_doc_number] => 07902043 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-08 [patent_title] => 'Method of producing bonded wafer' [patent_app_type] => utility [patent_app_number] => 11/855959 [patent_app_country] => US [patent_app_date] => 2007-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 4400 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/902/07902043.pdf [firstpage_image] =>[orig_patent_app_number] => 11855959 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4749313 [patent_doc_number] => 20080157384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'Alignment Key of Semiconductor Device and Method of Manufacturing the Same' [patent_app_type] => utility [patent_app_number] => 11/854739 [patent_app_country] => US [patent_app_date] => 2007-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2088 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157384.pdf [firstpage_image] =>[orig_patent_app_number] => 11854739 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 177801 [patent_doc_number] => 07655509 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-02 [patent_title] => 'Silicide-silicon oxide-semiconductor antifuse device and method of making' [patent_app_type] => utility [patent_app_number] => 11/898622 [patent_app_country] => US [patent_app_date] => 2007-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 7116 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/655/07655509.pdf [firstpage_image] =>[orig_patent_app_number] => 11898622 [rel_patent_id] =>[rel_patent_doc_number] =>)