
John D. Lee
Examiner (ID: 17114)
| Most Active Art Unit | 2501 |
| Art Unit(s) | 2874, 2606, 2507, 2501, 2504, 3621 |
| Total Applications | 2783 |
| Issued Applications | 2467 |
| Pending Applications | 118 |
| Abandoned Applications | 198 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 152342
[patent_doc_number] => 07683447
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-03-23
[patent_title] => 'MRAM device with continuous MTJ tunnel layers'
[patent_app_type] => utility
[patent_app_number] => 11/854478
[patent_app_country] => US
[patent_app_date] => 2007-09-12
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/683/07683447.pdf
[firstpage_image] =>[orig_patent_app_number] => 11854478
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/854478 | MRAM device with continuous MTJ tunnel layers | Sep 11, 2007 | Issued |
Array
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[patent_doc_number] => 20080006916
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-10
[patent_title] => 'Method of Manufacturing a Semiconductor Device'
[patent_app_type] => utility
[patent_app_number] => 11/853798
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 11853798
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/853798 | Method of Manufacturing a Semiconductor Device | Sep 10, 2007 | Abandoned |
Array
(
[id] => 5323588
[patent_doc_number] => 20090061578
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[patent_kind] => A1
[patent_issue_date] => 2009-03-05
[patent_title] => 'Method of Manufacturing a Semiconductor Microstructure'
[patent_app_type] => utility
[patent_app_number] => 11/847579
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[patent_app_date] => 2007-08-30
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/847579 | Method of Manufacturing a Semiconductor Microstructure | Aug 29, 2007 | Abandoned |
Array
(
[id] => 122755
[patent_doc_number] => 07704876
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[patent_kind] => B2
[patent_issue_date] => 2010-04-27
[patent_title] => 'Dual damascene interconnect structures having different materials for line and via conductors'
[patent_app_type] => utility
[patent_app_number] => 11/847657
[patent_app_country] => US
[patent_app_date] => 2007-08-30
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[patent_drawing_sheets_cnt] => 9
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[firstpage_image] =>[orig_patent_app_number] => 11847657
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/847657 | Dual damascene interconnect structures having different materials for line and via conductors | Aug 29, 2007 | Issued |
Array
(
[id] => 5230934
[patent_doc_number] => 20070293042
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[patent_kind] => A1
[patent_issue_date] => 2007-12-20
[patent_title] => 'SEMICONDUCTOR DIE WITH PROTECTIVE LAYER AND RELATED METHOD OF PROCESSING A SEMICONDUCTOR WAFER'
[patent_app_type] => utility
[patent_app_number] => 11/846749
[patent_app_country] => US
[patent_app_date] => 2007-08-29
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 11846749
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/846749 | Semiconductor die with protective layer and related method of processing a semiconductor wafer | Aug 28, 2007 | Issued |
Array
(
[id] => 5163078
[patent_doc_number] => 20070284659
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[patent_issue_date] => 2007-12-13
[patent_title] => 'METHOD OF FORMING HIGH VOLTAGE N-LDMOS TRANSISTORS HAVING SHALLOW TRENCH ISOLATION REGION WITH DRAIN EXTENSIONS'
[patent_app_type] => utility
[patent_app_number] => 11/844573
[patent_app_country] => US
[patent_app_date] => 2007-08-24
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/844573 | METHOD OF FORMING HIGH VOLTAGE N-LDMOS TRANSISTORS HAVING SHALLOW TRENCH ISOLATION REGION WITH DRAIN EXTENSIONS | Aug 23, 2007 | Abandoned |
Array
(
[id] => 4965132
[patent_doc_number] => 20080107952
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-08
[patent_title] => 'BIPOLAR SEPARATORS WITH IMPROVED FLUID DISTRIBUTION'
[patent_app_type] => utility
[patent_app_number] => 11/843063
[patent_app_country] => US
[patent_app_date] => 2007-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[pdf_file] => publications/A1/0107/20080107952.pdf
[firstpage_image] =>[orig_patent_app_number] => 11843063
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/843063 | Bipolar separators with improved fluid distribution | Aug 21, 2007 | Issued |
Array
(
[id] => 33210
[patent_doc_number] => 07785970
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-08-31
[patent_title] => 'Method of forming source and drain regions utilizing dual capping layers and split thermal processes'
[patent_app_type] => utility
[patent_app_number] => 11/841269
[patent_app_country] => US
[patent_app_date] => 2007-08-20
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[firstpage_image] =>[orig_patent_app_number] => 11841269
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/841269 | Method of forming source and drain regions utilizing dual capping layers and split thermal processes | Aug 19, 2007 | Issued |
Array
(
[id] => 4771957
[patent_doc_number] => 20080057615
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[patent_issue_date] => 2008-03-06
[patent_title] => 'MANUFACTURING METHOD OF PHOTOELECTRIC CONVERSION DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/840583
[patent_app_country] => US
[patent_app_date] => 2007-08-17
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[firstpage_image] =>[orig_patent_app_number] => 11840583
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/840583 | Manufacturing method of photoelectric conversion device | Aug 16, 2007 | Issued |
Array
(
[id] => 4669630
[patent_doc_number] => 20080044690
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-02-21
[patent_title] => 'Gas-liquid separator and fuel cell system having the same'
[patent_app_type] => utility
[patent_app_number] => 11/892007
[patent_app_country] => US
[patent_app_date] => 2007-08-17
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Array
(
[id] => 564729
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[patent_title] => 'Solid-state imaging device and method for fabricating same'
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[patent_app_number] => 11/891535
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Array
(
[id] => 4733936
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Array
(
[id] => 22146
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Array
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[patent_title] => 'Protective self-aligned buffer layers for damascene interconnects'
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Array
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Array
(
[id] => 5337442
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[patent_issue_date] => 2009-02-26
[patent_title] => 'Semiconductor Device Producing Method and Substrate Processing Apparatus'
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Array
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