Search

John D. Lee

Examiner (ID: 17114)

Most Active Art Unit
2501
Art Unit(s)
2874, 2606, 2507, 2501, 2504, 3621
Total Applications
2783
Issued Applications
2467
Pending Applications
118
Abandoned Applications
198

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 152342 [patent_doc_number] => 07683447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-23 [patent_title] => 'MRAM device with continuous MTJ tunnel layers' [patent_app_type] => utility [patent_app_number] => 11/854478 [patent_app_country] => US [patent_app_date] => 2007-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2591 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/683/07683447.pdf [firstpage_image] =>[orig_patent_app_number] => 11854478 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/854478
MRAM device with continuous MTJ tunnel layers Sep 11, 2007 Issued
Array ( [id] => 4795330 [patent_doc_number] => 20080006916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-10 [patent_title] => 'Method of Manufacturing a Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 11/853798 [patent_app_country] => US [patent_app_date] => 2007-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7324 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20080006916.pdf [firstpage_image] =>[orig_patent_app_number] => 11853798 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/853798
Method of Manufacturing a Semiconductor Device Sep 10, 2007 Abandoned
Array ( [id] => 5323588 [patent_doc_number] => 20090061578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'Method of Manufacturing a Semiconductor Microstructure' [patent_app_type] => utility [patent_app_number] => 11/847579 [patent_app_country] => US [patent_app_date] => 2007-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11962 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20090061578.pdf [firstpage_image] =>[orig_patent_app_number] => 11847579 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/847579
Method of Manufacturing a Semiconductor Microstructure Aug 29, 2007 Abandoned
Array ( [id] => 122755 [patent_doc_number] => 07704876 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-27 [patent_title] => 'Dual damascene interconnect structures having different materials for line and via conductors' [patent_app_type] => utility [patent_app_number] => 11/847657 [patent_app_country] => US [patent_app_date] => 2007-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 27 [patent_no_of_words] => 6291 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/704/07704876.pdf [firstpage_image] =>[orig_patent_app_number] => 11847657 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/847657
Dual damascene interconnect structures having different materials for line and via conductors Aug 29, 2007 Issued
Array ( [id] => 5230934 [patent_doc_number] => 20070293042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-20 [patent_title] => 'SEMICONDUCTOR DIE WITH PROTECTIVE LAYER AND RELATED METHOD OF PROCESSING A SEMICONDUCTOR WAFER' [patent_app_type] => utility [patent_app_number] => 11/846749 [patent_app_country] => US [patent_app_date] => 2007-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6903 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0293/20070293042.pdf [firstpage_image] =>[orig_patent_app_number] => 11846749 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/846749
Semiconductor die with protective layer and related method of processing a semiconductor wafer Aug 28, 2007 Issued
Array ( [id] => 5163078 [patent_doc_number] => 20070284659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'METHOD OF FORMING HIGH VOLTAGE N-LDMOS TRANSISTORS HAVING SHALLOW TRENCH ISOLATION REGION WITH DRAIN EXTENSIONS' [patent_app_type] => utility [patent_app_number] => 11/844573 [patent_app_country] => US [patent_app_date] => 2007-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3315 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0284/20070284659.pdf [firstpage_image] =>[orig_patent_app_number] => 11844573 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/844573
METHOD OF FORMING HIGH VOLTAGE N-LDMOS TRANSISTORS HAVING SHALLOW TRENCH ISOLATION REGION WITH DRAIN EXTENSIONS Aug 23, 2007 Abandoned
Array ( [id] => 4965132 [patent_doc_number] => 20080107952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'BIPOLAR SEPARATORS WITH IMPROVED FLUID DISTRIBUTION' [patent_app_type] => utility [patent_app_number] => 11/843063 [patent_app_country] => US [patent_app_date] => 2007-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4485 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20080107952.pdf [firstpage_image] =>[orig_patent_app_number] => 11843063 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/843063
Bipolar separators with improved fluid distribution Aug 21, 2007 Issued
Array ( [id] => 33210 [patent_doc_number] => 07785970 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-31 [patent_title] => 'Method of forming source and drain regions utilizing dual capping layers and split thermal processes' [patent_app_type] => utility [patent_app_number] => 11/841269 [patent_app_country] => US [patent_app_date] => 2007-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 6511 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/785/07785970.pdf [firstpage_image] =>[orig_patent_app_number] => 11841269 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/841269
Method of forming source and drain regions utilizing dual capping layers and split thermal processes Aug 19, 2007 Issued
Array ( [id] => 4771957 [patent_doc_number] => 20080057615 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'MANUFACTURING METHOD OF PHOTOELECTRIC CONVERSION DEVICE' [patent_app_type] => utility [patent_app_number] => 11/840583 [patent_app_country] => US [patent_app_date] => 2007-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7620 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20080057615.pdf [firstpage_image] =>[orig_patent_app_number] => 11840583 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/840583
Manufacturing method of photoelectric conversion device Aug 16, 2007 Issued
Array ( [id] => 4669630 [patent_doc_number] => 20080044690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-21 [patent_title] => 'Gas-liquid separator and fuel cell system having the same' [patent_app_type] => utility [patent_app_number] => 11/892007 [patent_app_country] => US [patent_app_date] => 2007-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3617 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20080044690.pdf [firstpage_image] =>[orig_patent_app_number] => 11892007 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/892007
Gas-liquid separator and fuel cell system having the same Aug 16, 2007 Issued
Array ( [id] => 564729 [patent_doc_number] => 07465598 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-16 [patent_title] => 'Solid-state imaging device and method for fabricating same' [patent_app_type] => utility [patent_app_number] => 11/891535 [patent_app_country] => US [patent_app_date] => 2007-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5594 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/465/07465598.pdf [firstpage_image] =>[orig_patent_app_number] => 11891535 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/891535
Solid-state imaging device and method for fabricating same Aug 9, 2007 Issued
Array ( [id] => 4733936 [patent_doc_number] => 20080050915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/882663 [patent_app_country] => US [patent_app_date] => 2007-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3396 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20080050915.pdf [firstpage_image] =>[orig_patent_app_number] => 11882663 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/882663
Method for manufacturing semiconductor device Aug 2, 2007 Abandoned
Array ( [id] => 22146 [patent_doc_number] => 07799608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-21 [patent_title] => 'Die stacking apparatus and method' [patent_app_type] => utility [patent_app_number] => 11/832519 [patent_app_country] => US [patent_app_date] => 2007-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3800 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/799/07799608.pdf [firstpage_image] =>[orig_patent_app_number] => 11832519 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/832519
Die stacking apparatus and method Jul 31, 2007 Issued
Array ( [id] => 256333 [patent_doc_number] => 07576006 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-08-18 [patent_title] => 'Protective self-aligned buffer layers for damascene interconnects' [patent_app_type] => utility [patent_app_number] => 11/888323 [patent_app_country] => US [patent_app_date] => 2007-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 17501 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/576/07576006.pdf [firstpage_image] =>[orig_patent_app_number] => 11888323 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/888323
Protective self-aligned buffer layers for damascene interconnects Jul 29, 2007 Issued
Array ( [id] => 4619161 [patent_doc_number] => 07998880 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-16 [patent_title] => 'Low k dielectric CVD film formation process with in-situ imbedded nanolayers to improve mechanical properties' [patent_app_type] => utility [patent_app_number] => 11/830425 [patent_app_country] => US [patent_app_date] => 2007-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 8100 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/998/07998880.pdf [firstpage_image] =>[orig_patent_app_number] => 11830425 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/830425
Low k dielectric CVD film formation process with in-situ imbedded nanolayers to improve mechanical properties Jul 29, 2007 Issued
Array ( [id] => 5337442 [patent_doc_number] => 20090053906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-26 [patent_title] => 'Semiconductor Device Producing Method and Substrate Processing Apparatus' [patent_app_type] => utility [patent_app_number] => 12/087779 [patent_app_country] => US [patent_app_date] => 2007-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8456 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20090053906.pdf [firstpage_image] =>[orig_patent_app_number] => 12087779 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/087779
Semiconductor device producing method and substrate processing apparatus Jul 18, 2007 Issued
Array ( [id] => 5016280 [patent_doc_number] => 20070259489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-08 [patent_title] => 'Method of forming transistor structure having stressed regions of opposite types' [patent_app_type] => utility [patent_app_number] => 11/879065 [patent_app_country] => US [patent_app_date] => 2007-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3681 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20070259489.pdf [firstpage_image] =>[orig_patent_app_number] => 11879065 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/879065
Method of forming transistor structure having stressed regions of opposite types Jul 15, 2007 Issued
Array ( [id] => 53853 [patent_doc_number] => 07767558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-03 [patent_title] => 'Method of crystallizing amorphous silicon and device fabricated using the same' [patent_app_type] => utility [patent_app_number] => 11/822297 [patent_app_country] => US [patent_app_date] => 2007-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3271 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 397 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/767/07767558.pdf [firstpage_image] =>[orig_patent_app_number] => 11822297 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/822297
Method of crystallizing amorphous silicon and device fabricated using the same Jul 2, 2007 Issued
Array ( [id] => 5210505 [patent_doc_number] => 20070249089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'Method of making circuitized substrate with internal organic memory device' [patent_app_type] => utility [patent_app_number] => 11/808596 [patent_app_country] => US [patent_app_date] => 2007-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8250 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0249/20070249089.pdf [firstpage_image] =>[orig_patent_app_number] => 11808596 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/808596
Method of making circuitized substrate with internal organic memory device Jun 11, 2007 Issued
Array ( [id] => 5225152 [patent_doc_number] => 20070254418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'Methods of fabricating nitride-based transistors with a cap layer and a recessed gate' [patent_app_type] => utility [patent_app_number] => 11/810026 [patent_app_country] => US [patent_app_date] => 2007-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7192 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20070254418.pdf [firstpage_image] =>[orig_patent_app_number] => 11810026 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/810026
Methods of fabricating nitride-based transistors with a cap layer and a recessed gate Jun 3, 2007 Issued
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