Search

John D. Lee

Examiner (ID: 17114)

Most Active Art Unit
2501
Art Unit(s)
2874, 2606, 2507, 2501, 2504, 3621
Total Applications
2783
Issued Applications
2467
Pending Applications
118
Abandoned Applications
198

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8270081 [patent_doc_number] => 08211584 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-03 [patent_title] => 'Metal separator for fuel cell and fuel cell stack having the same' [patent_app_type] => utility [patent_app_number] => 12/445576 [patent_app_country] => US [patent_app_date] => 2007-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6321 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12445576 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/445576
Metal separator for fuel cell and fuel cell stack having the same Jun 3, 2007 Issued
Array ( [id] => 83543 [patent_doc_number] => 07741215 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-22 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/809478 [patent_app_country] => US [patent_app_date] => 2007-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 28 [patent_no_of_words] => 6685 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/741/07741215.pdf [firstpage_image] =>[orig_patent_app_number] => 11809478 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/809478
Semiconductor device and method for manufacturing the same May 31, 2007 Issued
Array ( [id] => 4752678 [patent_doc_number] => 20080160753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'Method of forming metal wire in semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/801498 [patent_app_country] => US [patent_app_date] => 2007-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2685 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20080160753.pdf [firstpage_image] =>[orig_patent_app_number] => 11801498 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/801498
Method of forming metal wire in semiconductor device May 9, 2007 Issued
Array ( [id] => 5046142 [patent_doc_number] => 20070264815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-15 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/797249 [patent_app_country] => US [patent_app_date] => 2007-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5039 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0264/20070264815.pdf [firstpage_image] =>[orig_patent_app_number] => 11797249 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/797249
Method for fabricating semiconductor device May 1, 2007 Abandoned
Array ( [id] => 236552 [patent_doc_number] => 07595533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-29 [patent_title] => 'Thin film semiconductor device and manufacturing method' [patent_app_type] => utility [patent_app_number] => 11/740226 [patent_app_country] => US [patent_app_date] => 2007-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 30 [patent_no_of_words] => 16057 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/595/07595533.pdf [firstpage_image] =>[orig_patent_app_number] => 11740226 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/740226
Thin film semiconductor device and manufacturing method Apr 24, 2007 Issued
Array ( [id] => 5569895 [patent_doc_number] => 20090253273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-08 [patent_title] => 'METHOD OF HEAT-TREATING SEMICONDUCTOR' [patent_app_type] => utility [patent_app_number] => 12/305180 [patent_app_country] => US [patent_app_date] => 2007-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7709 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20090253273.pdf [firstpage_image] =>[orig_patent_app_number] => 12305180 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/305180
METHOD OF HEAT-TREATING SEMICONDUCTOR Apr 24, 2007 Abandoned
Array ( [id] => 5113112 [patent_doc_number] => 20070197027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'FORMATION OF BORIDE BARRIER LAYERS USING CHEMISORPTION TECHNIQUES' [patent_app_type] => utility [patent_app_number] => 11/739545 [patent_app_country] => US [patent_app_date] => 2007-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4577 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20070197027.pdf [firstpage_image] =>[orig_patent_app_number] => 11739545 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/739545
Formation of boride barrier layers using chemisorption techniques Apr 23, 2007 Issued
Array ( [id] => 5113113 [patent_doc_number] => 20070197028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'FORMATION OF BORIDE BARRIER LAYERS USING CHEMISORPTION TECHNIQUES' [patent_app_type] => utility [patent_app_number] => 11/739549 [patent_app_country] => US [patent_app_date] => 2007-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4579 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20070197028.pdf [firstpage_image] =>[orig_patent_app_number] => 11739549 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/739549
Formation of boride barrier layers using chemisorption techniques Apr 23, 2007 Issued
Array ( [id] => 5026290 [patent_doc_number] => 20070267736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-22 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/734996 [patent_app_country] => US [patent_app_date] => 2007-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 18745 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20070267736.pdf [firstpage_image] =>[orig_patent_app_number] => 11734996 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/734996
Semiconductor device and method of manufacturing the same Apr 12, 2007 Issued
Array ( [id] => 5110498 [patent_doc_number] => 20070194413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Method for manufacturing semiconductor substrate' [patent_app_type] => utility [patent_app_number] => 11/783765 [patent_app_country] => US [patent_app_date] => 2007-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4938 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20070194413.pdf [firstpage_image] =>[orig_patent_app_number] => 11783765 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/783765
Method for manufacturing semiconductor substrate Apr 11, 2007 Issued
Array ( [id] => 359640 [patent_doc_number] => 07485519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-03 [patent_title] => 'After gate fabrication of field effect transistor having tensile and compressive regions' [patent_app_type] => utility [patent_app_number] => 11/693786 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4706 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/485/07485519.pdf [firstpage_image] =>[orig_patent_app_number] => 11693786 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/693786
After gate fabrication of field effect transistor having tensile and compressive regions Mar 29, 2007 Issued
Array ( [id] => 908208 [patent_doc_number] => 07332774 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-19 [patent_title] => 'Multiple-gate MOS transistor and a method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/727268 [patent_app_country] => US [patent_app_date] => 2007-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 32 [patent_no_of_words] => 4733 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/332/07332774.pdf [firstpage_image] =>[orig_patent_app_number] => 11727268 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/727268
Multiple-gate MOS transistor and a method of manufacturing the same Mar 25, 2007 Issued
Array ( [id] => 122750 [patent_doc_number] => 07704873 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-04-27 [patent_title] => 'Protective self-aligned buffer layers for damascene interconnects' [patent_app_type] => utility [patent_app_number] => 11/726363 [patent_app_country] => US [patent_app_date] => 2007-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 17461 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/704/07704873.pdf [firstpage_image] =>[orig_patent_app_number] => 11726363 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/726363
Protective self-aligned buffer layers for damascene interconnects Mar 19, 2007 Issued
Array ( [id] => 102090 [patent_doc_number] => 07727880 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-06-01 [patent_title] => 'Protective self-aligned buffer layers for damascene interconnects' [patent_app_type] => utility [patent_app_number] => 11/709294 [patent_app_country] => US [patent_app_date] => 2007-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 15101 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/727/07727880.pdf [firstpage_image] =>[orig_patent_app_number] => 11709294 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/709294
Protective self-aligned buffer layers for damascene interconnects Feb 19, 2007 Issued
Array ( [id] => 102091 [patent_doc_number] => 07727881 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-06-01 [patent_title] => 'Protective self-aligned buffer layers for damascene interconnects' [patent_app_type] => utility [patent_app_number] => 11/709293 [patent_app_country] => US [patent_app_date] => 2007-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 15088 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/727/07727881.pdf [firstpage_image] =>[orig_patent_app_number] => 11709293 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/709293
Protective self-aligned buffer layers for damascene interconnects Feb 19, 2007 Issued
Array ( [id] => 303966 [patent_doc_number] => 07535106 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-19 [patent_title] => 'Wiring glass substrate for connecting a semiconductor chip to a printed wiring substrate and a semiconductor module having the wiring glass substrate' [patent_app_type] => utility [patent_app_number] => 11/657280 [patent_app_country] => US [patent_app_date] => 2007-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 42 [patent_no_of_words] => 28902 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/535/07535106.pdf [firstpage_image] =>[orig_patent_app_number] => 11657280 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/657280
Wiring glass substrate for connecting a semiconductor chip to a printed wiring substrate and a semiconductor module having the wiring glass substrate Jan 23, 2007 Issued
Array ( [id] => 4651605 [patent_doc_number] => 20080038861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'Support with integrated deposit of gas absorbing material for manufacturing microelectronic microoptoelectronic or micromechanical devices' [patent_app_type] => utility [patent_app_number] => 11/657706 [patent_app_country] => US [patent_app_date] => 2007-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4120 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20080038861.pdf [firstpage_image] =>[orig_patent_app_number] => 11657706 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/657706
Support with integrated deposit of gas absorbing material for manufacturing microelectronic microoptoelectronic or micromechanical devices Jan 22, 2007 Issued
Array ( [id] => 5256799 [patent_doc_number] => 20070210431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'Support with integrated deposit of gas absorbing material for manufacturing microelectronic microoptoelectronic or micromechanical devices' [patent_app_type] => utility [patent_app_number] => 11/657703 [patent_app_country] => US [patent_app_date] => 2007-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4122 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20070210431.pdf [firstpage_image] =>[orig_patent_app_number] => 11657703 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/657703
Support with integrated deposit of gas absorbing material for manufacturing microelectronic, microoptoelectronic or micromechanical devices Jan 22, 2007 Issued
Array ( [id] => 4971408 [patent_doc_number] => 20070111410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'HIGH MOBILITY PLANE FINFETS WITH EQUAL DRIVE STRENGTH' [patent_app_type] => utility [patent_app_number] => 11/622169 [patent_app_country] => US [patent_app_date] => 2007-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2759 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20070111410.pdf [firstpage_image] =>[orig_patent_app_number] => 11622169 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/622169
High mobility plane FinFETs with equal drive strength Jan 10, 2007 Issued
Array ( [id] => 7689457 [patent_doc_number] => 20070105241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Ferromagnetic liner for conductive lines of magnetic memory cells' [patent_app_type] => utility [patent_app_number] => 11/644792 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7894 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20070105241.pdf [firstpage_image] =>[orig_patent_app_number] => 11644792 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/644792
Ferromagnetic liner for conductive lines of magnetic memory cells Dec 21, 2006 Issued
Menu