
John D. Lee
Examiner (ID: 17114)
| Most Active Art Unit | 2501 |
| Art Unit(s) | 2874, 2606, 2507, 2501, 2504, 3621 |
| Total Applications | 2783 |
| Issued Applications | 2467 |
| Pending Applications | 118 |
| Abandoned Applications | 198 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6470419
[patent_doc_number] => 20100040911
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-02-18
[patent_title] => 'FUEL CELL FLOW FIELD HAVING STRONG, CHEMICALLY STABLE METAL BIPOLAR PLATES'
[patent_app_type] => utility
[patent_app_number] => 12/514507
[patent_app_country] => US
[patent_app_date] => 2006-12-08
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0040/20100040911.pdf
[firstpage_image] =>[orig_patent_app_number] => 12514507
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/514507 | Fuel cell flow field having strong, chemically stable metal bipolar plates | Dec 7, 2006 | Issued |
Array
(
[id] => 4833513
[patent_doc_number] => 20080132060
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[patent_kind] => A1
[patent_issue_date] => 2008-06-05
[patent_title] => 'CONTACT BARRIER LAYER DEPOSITION PROCESS'
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[patent_app_date] => 2006-11-30
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/565355 | CONTACT BARRIER LAYER DEPOSITION PROCESS | Nov 29, 2006 | Abandoned |
Array
(
[id] => 5077038
[patent_doc_number] => 20070120262
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[patent_kind] => A1
[patent_issue_date] => 2007-05-31
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/564175
[patent_app_country] => US
[patent_app_date] => 2006-11-28
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Array
(
[id] => 4825904
[patent_doc_number] => 20080124859
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[patent_kind] => A1
[patent_issue_date] => 2008-05-29
[patent_title] => 'Methods of Forming CMOS Integrated Circuits Using Gate Sidewall Spacer Reduction Techniques'
[patent_app_type] => utility
[patent_app_number] => 11/563476
[patent_app_country] => US
[patent_app_date] => 2006-11-27
[patent_effective_date] => 0000-00-00
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Array
(
[id] => 4820756
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[patent_issue_date] => 2008-05-29
[patent_title] => 'APPLICATIONS OF POLYCRYSTALLINE WAFERS'
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[patent_app_date] => 2006-11-27
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Array
(
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[patent_issue_date] => 2008-05-06
[patent_title] => 'Method for fabricating a nano-imprinting mold'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/601084 | Method for fabricating a nano-imprinting mold | Nov 15, 2006 | Issued |
Array
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[patent_title] => 'Wafer encapsulated microelectromechanical structure and method of manufacturing same'
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[patent_app_country] => US
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Array
(
[id] => 281750
[patent_doc_number] => 07553750
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[patent_kind] => B2
[patent_issue_date] => 2009-06-30
[patent_title] => 'Method for fabricating electrical conductive structure of circuit board'
[patent_app_type] => utility
[patent_app_number] => 11/559576
[patent_app_country] => US
[patent_app_date] => 2006-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/559576 | Method for fabricating electrical conductive structure of circuit board | Nov 13, 2006 | Issued |
Array
(
[id] => 5043792
[patent_doc_number] => 20070262463
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[patent_issue_date] => 2007-11-15
[patent_title] => 'Semiconductor substrate-based interconnection assembly for semiconductor device bearing external elements'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/585655 | Semiconductor substrate-based interconnection assembly for semiconductor device bearing external elements | Oct 23, 2006 | Abandoned |
Array
(
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[patent_title] => 'Semiconductor device and method for fabricating the same'
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/550966 | Sub-lithographic nano interconnect structures, and method for forming same | Oct 18, 2006 | Issued |
Array
(
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[patent_title] => 'Semiconductor device, dicing saw and method for manufacturing the semiconductor device'
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Array
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Array
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Array
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Array
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[patent_title] => 'MOSFET STRUCTURE WITH MULTIPLE SELF-ALIGNED SILICIDE CONTACTS'
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Array
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Array
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