Search

John D. Lee

Examiner (ID: 17114)

Most Active Art Unit
2501
Art Unit(s)
2874, 2606, 2507, 2501, 2504, 3621
Total Applications
2783
Issued Applications
2467
Pending Applications
118
Abandoned Applications
198

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6470419 [patent_doc_number] => 20100040911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-18 [patent_title] => 'FUEL CELL FLOW FIELD HAVING STRONG, CHEMICALLY STABLE METAL BIPOLAR PLATES' [patent_app_type] => utility [patent_app_number] => 12/514507 [patent_app_country] => US [patent_app_date] => 2006-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1863 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20100040911.pdf [firstpage_image] =>[orig_patent_app_number] => 12514507 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/514507
Fuel cell flow field having strong, chemically stable metal bipolar plates Dec 7, 2006 Issued
Array ( [id] => 4833513 [patent_doc_number] => 20080132060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'CONTACT BARRIER LAYER DEPOSITION PROCESS' [patent_app_type] => utility [patent_app_number] => 11/565355 [patent_app_country] => US [patent_app_date] => 2006-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5568 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20080132060.pdf [firstpage_image] =>[orig_patent_app_number] => 11565355 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/565355
CONTACT BARRIER LAYER DEPOSITION PROCESS Nov 29, 2006 Abandoned
Array ( [id] => 5077038 [patent_doc_number] => 20070120262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-31 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/564175 [patent_app_country] => US [patent_app_date] => 2006-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3043 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20070120262.pdf [firstpage_image] =>[orig_patent_app_number] => 11564175 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/564175
Semiconductor device and method for manufacturing the same Nov 27, 2006 Issued
Array ( [id] => 4825904 [patent_doc_number] => 20080124859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'Methods of Forming CMOS Integrated Circuits Using Gate Sidewall Spacer Reduction Techniques' [patent_app_type] => utility [patent_app_number] => 11/563476 [patent_app_country] => US [patent_app_date] => 2006-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1973 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20080124859.pdf [firstpage_image] =>[orig_patent_app_number] => 11563476 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/563476
Methods of Forming CMOS Integrated Circuits Using Gate Sidewall Spacer Reduction Techniques Nov 26, 2006 Abandoned
Array ( [id] => 4820756 [patent_doc_number] => 20080122042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'APPLICATIONS OF POLYCRYSTALLINE WAFERS' [patent_app_type] => utility [patent_app_number] => 11/563626 [patent_app_country] => US [patent_app_date] => 2006-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3099 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20080122042.pdf [firstpage_image] =>[orig_patent_app_number] => 11563626 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/563626
APPLICATIONS OF POLYCRYSTALLINE WAFERS Nov 26, 2006 Abandoned
Array ( [id] => 864764 [patent_doc_number] => 07368395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-06 [patent_title] => 'Method for fabricating a nano-imprinting mold' [patent_app_type] => utility [patent_app_number] => 11/601084 [patent_app_country] => US [patent_app_date] => 2006-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 7890 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/368/07368395.pdf [firstpage_image] =>[orig_patent_app_number] => 11601084 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/601084
Method for fabricating a nano-imprinting mold Nov 15, 2006 Issued
Array ( [id] => 5157396 [patent_doc_number] => 20070170440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-26 [patent_title] => 'Wafer encapsulated microelectromechanical structure and method of manufacturing same' [patent_app_type] => utility [patent_app_number] => 11/600860 [patent_app_country] => US [patent_app_date] => 2006-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 210 [patent_figures_cnt] => 210 [patent_no_of_words] => 18533 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20070170440.pdf [firstpage_image] =>[orig_patent_app_number] => 11600860 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/600860
Wafer encapsulated microelectromechanical structure and method of manufacturing same Nov 15, 2006 Abandoned
Array ( [id] => 281750 [patent_doc_number] => 07553750 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-30 [patent_title] => 'Method for fabricating electrical conductive structure of circuit board' [patent_app_type] => utility [patent_app_number] => 11/559576 [patent_app_country] => US [patent_app_date] => 2006-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 21 [patent_no_of_words] => 2759 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/553/07553750.pdf [firstpage_image] =>[orig_patent_app_number] => 11559576 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/559576
Method for fabricating electrical conductive structure of circuit board Nov 13, 2006 Issued
Array ( [id] => 5043792 [patent_doc_number] => 20070262463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-15 [patent_title] => 'Semiconductor substrate-based interconnection assembly for semiconductor device bearing external elements' [patent_app_type] => utility [patent_app_number] => 11/585655 [patent_app_country] => US [patent_app_date] => 2006-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4589 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20070262463.pdf [firstpage_image] =>[orig_patent_app_number] => 11585655 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/585655
Semiconductor substrate-based interconnection assembly for semiconductor device bearing external elements Oct 23, 2006 Abandoned
Array ( [id] => 5031673 [patent_doc_number] => 20070096212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/583846 [patent_app_country] => US [patent_app_date] => 2006-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8848 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20070096212.pdf [firstpage_image] =>[orig_patent_app_number] => 11583846 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/583846
Semiconductor device and method for fabricating the same Oct 19, 2006 Abandoned
Array ( [id] => 281760 [patent_doc_number] => 07553760 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-30 [patent_title] => 'Sub-lithographic nano interconnect structures, and method for forming same' [patent_app_type] => utility [patent_app_number] => 11/550966 [patent_app_country] => US [patent_app_date] => 2006-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 36 [patent_no_of_words] => 8000 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/553/07553760.pdf [firstpage_image] =>[orig_patent_app_number] => 11550966 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/550966
Sub-lithographic nano interconnect structures, and method for forming same Oct 18, 2006 Issued
Array ( [id] => 5186133 [patent_doc_number] => 20070164440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Semiconductor device, dicing saw and method for manufacturing the semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/545426 [patent_app_country] => US [patent_app_date] => 2006-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3966 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20070164440.pdf [firstpage_image] =>[orig_patent_app_number] => 11545426 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/545426
Semiconductor device, dicing saw and method for manufacturing the semiconductor device Oct 10, 2006 Abandoned
Array ( [id] => 195866 [patent_doc_number] => 07635644 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-22 [patent_title] => 'Semiconductor device including metal interconnection and method for forming metal interconnection' [patent_app_type] => utility [patent_app_number] => 11/544756 [patent_app_country] => US [patent_app_date] => 2006-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 25 [patent_no_of_words] => 5506 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/635/07635644.pdf [firstpage_image] =>[orig_patent_app_number] => 11544756 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/544756
Semiconductor device including metal interconnection and method for forming metal interconnection Oct 9, 2006 Issued
Array ( [id] => 5049083 [patent_doc_number] => 20070029627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-08 [patent_title] => 'Reducing the dielectric constant of a portion of a gate dielectric' [patent_app_type] => utility [patent_app_number] => 11/545313 [patent_app_country] => US [patent_app_date] => 2006-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4951 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20070029627.pdf [firstpage_image] =>[orig_patent_app_number] => 11545313 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/545313
Reducing the dielectric constant of a portion of a gate dielectric Oct 9, 2006 Abandoned
Array ( [id] => 5157544 [patent_doc_number] => 20070170588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-26 [patent_title] => 'Connection structure and fabrication method for the same' [patent_app_type] => utility [patent_app_number] => 11/544646 [patent_app_country] => US [patent_app_date] => 2006-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7773 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20070170588.pdf [firstpage_image] =>[orig_patent_app_number] => 11544646 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/544646
Connection structure and fabrication method for the same Oct 9, 2006 Abandoned
Array ( [id] => 4982978 [patent_doc_number] => 20070087536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'MOSFET STRUCTURE WITH MULTIPLE SELF-ALIGNED SILICIDE CONTACTS' [patent_app_type] => utility [patent_app_number] => 11/539236 [patent_app_country] => US [patent_app_date] => 2006-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5093 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20070087536.pdf [firstpage_image] =>[orig_patent_app_number] => 11539236 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/539236
MOSFET structure with multiple self-aligned silicide contacts Oct 5, 2006 Issued
Array ( [id] => 7801019 [patent_doc_number] => 08129289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-06 [patent_title] => 'Method to deposit conformal low temperature SiO2' [patent_app_type] => utility [patent_app_number] => 11/543515 [patent_app_country] => US [patent_app_date] => 2006-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 6168 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/129/08129289.pdf [firstpage_image] =>[orig_patent_app_number] => 11543515 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/543515
Method to deposit conformal low temperature SiO2 Oct 4, 2006 Issued
Array ( [id] => 236279 [patent_doc_number] => 07595260 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-29 [patent_title] => 'Doped elongated semiconductors, growing such semiconductors, devices including such semiconductors, and fabricating such devices' [patent_app_type] => utility [patent_app_number] => 11/543326 [patent_app_country] => US [patent_app_date] => 2006-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 90 [patent_no_of_words] => 40047 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/595/07595260.pdf [firstpage_image] =>[orig_patent_app_number] => 11543326 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/543326
Doped elongated semiconductors, growing such semiconductors, devices including such semiconductors, and fabricating such devices Oct 3, 2006 Issued
Array ( [id] => 160021 [patent_doc_number] => 07675063 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-09 [patent_title] => 'Liquid crystal display device and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/542248 [patent_app_country] => US [patent_app_date] => 2006-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 36 [patent_no_of_words] => 5651 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/675/07675063.pdf [firstpage_image] =>[orig_patent_app_number] => 11542248 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/542248
Liquid crystal display device and method of fabricating the same Oct 3, 2006 Issued
Array ( [id] => 10864630 [patent_doc_number] => 08890338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-18 [patent_title] => 'Method of identifying and/or programming an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/535866 [patent_app_country] => US [patent_app_date] => 2006-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2301 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11535866 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/535866
Method of identifying and/or programming an integrated circuit Sep 26, 2006 Issued
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