
John D. Lee
Examiner (ID: 17114)
| Most Active Art Unit | 2501 |
| Art Unit(s) | 2874, 2606, 2507, 2501, 2504, 3621 |
| Total Applications | 2783 |
| Issued Applications | 2467 |
| Pending Applications | 118 |
| Abandoned Applications | 198 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4938935
[patent_doc_number] => 20080076254
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-27
[patent_title] => 'Blanket resist to protect active side of semiconductor'
[patent_app_type] => utility
[patent_app_number] => 11/528255
[patent_app_country] => US
[patent_app_date] => 2006-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 3099
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[pdf_file] => publications/A1/0076/20080076254.pdf
[firstpage_image] =>[orig_patent_app_number] => 11528255
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/528255 | Blanket resist to protect active side of semiconductor | Sep 26, 2006 | Issued |
Array
(
[id] => 5107102
[patent_doc_number] => 20070065980
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-22
[patent_title] => 'Method of manufacturing semiconductor chip'
[patent_app_type] => utility
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[patent_app_country] => US
[patent_app_date] => 2006-09-20
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[firstpage_image] =>[orig_patent_app_number] => 11523576
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/523576 | Method of manufacturing semiconductor chip | Sep 19, 2006 | Issued |
Array
(
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[patent_doc_number] => 20070063350
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[patent_kind] => A1
[patent_issue_date] => 2007-03-22
[patent_title] => 'Semiconductor device and method for designing same'
[patent_app_type] => utility
[patent_app_number] => 11/522436
[patent_app_country] => US
[patent_app_date] => 2006-09-18
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[patent_drawing_sheets_cnt] => 7
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/522436 | Semiconductor device and method for designing same | Sep 17, 2006 | Issued |
Array
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[id] => 4919351
[patent_doc_number] => 20080067663
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[patent_kind] => A1
[patent_issue_date] => 2008-03-20
[patent_title] => 'Wafer level chip package and a method of fabricating thereof'
[patent_app_type] => utility
[patent_app_number] => 11/522885
[patent_app_country] => US
[patent_app_date] => 2006-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[firstpage_image] =>[orig_patent_app_number] => 11522885
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/522885 | Wafer level chip package and a method of fabricating thereof | Sep 17, 2006 | Issued |
Array
(
[id] => 5552134
[patent_doc_number] => 20090286120
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[patent_kind] => A1
[patent_issue_date] => 2009-11-19
[patent_title] => 'CASING FOR FUEL BATTERY AND FUEL BATTERY USING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/066937
[patent_app_country] => US
[patent_app_date] => 2006-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[firstpage_image] =>[orig_patent_app_number] => 12066937
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/066937 | Casing for fuel battery and fuel battery using the same | Sep 14, 2006 | Issued |
Array
(
[id] => 292333
[patent_doc_number] => 07544623
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-06-09
[patent_title] => 'Method for fabricating a contact hole'
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[patent_app_number] => 11/530886
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[pdf_file] => patents/07/544/07544623.pdf
[firstpage_image] =>[orig_patent_app_number] => 11530886
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/530886 | Method for fabricating a contact hole | Sep 10, 2006 | Issued |
Array
(
[id] => 220951
[patent_doc_number] => 07608497
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[patent_issue_date] => 2009-10-27
[patent_title] => 'Passivated tiered gate structure transistor and fabrication method'
[patent_app_type] => utility
[patent_app_number] => 11/517685
[patent_app_country] => US
[patent_app_date] => 2006-09-08
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/608/07608497.pdf
[firstpage_image] =>[orig_patent_app_number] => 11517685
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/517685 | Passivated tiered gate structure transistor and fabrication method | Sep 7, 2006 | Issued |
Array
(
[id] => 5183103
[patent_doc_number] => 20070054457
[patent_country] => US
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[patent_issue_date] => 2007-03-08
[patent_title] => 'Method of fabricating MOS transistor having epitaxial region'
[patent_app_type] => utility
[patent_app_number] => 11/517246
[patent_app_country] => US
[patent_app_date] => 2006-09-08
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[pdf_file] => publications/A1/0054/20070054457.pdf
[firstpage_image] =>[orig_patent_app_number] => 11517246
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/517246 | Method of fabricating MOS transistor having epitaxial region | Sep 7, 2006 | Issued |
Array
(
[id] => 142710
[patent_doc_number] => 07687911
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-03-30
[patent_title] => 'Silicon-alloy based barrier layers for integrated circuit metal interconnects'
[patent_app_type] => utility
[patent_app_number] => 11/517736
[patent_app_country] => US
[patent_app_date] => 2006-09-07
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[pdf_file] => patents/07/687/07687911.pdf
[firstpage_image] =>[orig_patent_app_number] => 11517736
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/517736 | Silicon-alloy based barrier layers for integrated circuit metal interconnects | Sep 6, 2006 | Issued |
Array
(
[id] => 4768680
[patent_doc_number] => 20080054336
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-06
[patent_title] => 'Scalable Electrically Eraseable And Programmable Memory'
[patent_app_type] => utility
[patent_app_number] => 11/470245
[patent_app_country] => US
[patent_app_date] => 2006-09-05
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0054/20080054336.pdf
[firstpage_image] =>[orig_patent_app_number] => 11470245
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/470245 | Scalable electrically eraseable and programmable memory | Sep 4, 2006 | Issued |
Array
(
[id] => 270848
[patent_doc_number] => 07564084
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-07-21
[patent_title] => 'Dual-gate dynamic random access memory device having vertical channel transistors and method of fabricating the same'
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[patent_app_number] => 11/513945
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/513945 | Dual-gate dynamic random access memory device having vertical channel transistors and method of fabricating the same | Aug 30, 2006 | Issued |
Array
(
[id] => 7597737
[patent_doc_number] => 07618840
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[patent_issue_date] => 2009-11-17
[patent_title] => 'Sublithographic contact structure, in particular for a phase change memory cell, and fabrication process thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/468153 | Sublithographic contact structure, in particular for a phase change memory cell, and fabrication process thereof | Aug 28, 2006 | Issued |
Array
(
[id] => 5145630
[patent_doc_number] => 20070045684
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[patent_title] => 'Image sensor and method for fabricating the same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/508956 | Image sensor and method for fabricating the same | Aug 23, 2006 | Issued |
Array
(
[id] => 5730277
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[patent_title] => 'METHOD OF FORMING A RELIABLE HIGH PERFORMANCE CAPACITOR USING AN ISOTROPIC ETCHING PROCESS'
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Array
(
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[patent_title] => 'Manufacturing method of semiconductor device'
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Array
(
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[patent_title] => 'Semiconductor memory integrated circuit and its manufacturing method'
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Array
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Array
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Array
(
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/441386 | Trench-gate field effect transistors and methods of forming the same | May 23, 2006 | Issued |