
John D. Lee
Examiner (ID: 17114)
| Most Active Art Unit | 2501 |
| Art Unit(s) | 2874, 2606, 2507, 2501, 2504, 3621 |
| Total Applications | 2783 |
| Issued Applications | 2467 |
| Pending Applications | 118 |
| Abandoned Applications | 198 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5242320
[patent_doc_number] => 20070020815
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-25
[patent_title] => 'Process for exposing solder bumps on an underfill coated semiconductor'
[patent_app_type] => utility
[patent_app_number] => 11/168236
[patent_app_country] => US
[patent_app_date] => 2005-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2987
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0020/20070020815.pdf
[firstpage_image] =>[orig_patent_app_number] => 11168236
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/168236 | Process for exposing solder bumps on an underfill coated semiconductor | Jul 21, 2005 | Issued |
Array
(
[id] => 852966
[patent_doc_number] => 07378350
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-05-27
[patent_title] => 'Formation of low resistance via contacts in interconnect structures'
[patent_app_type] => utility
[patent_app_number] => 11/182445
[patent_app_country] => US
[patent_app_date] => 2005-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3822
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/378/07378350.pdf
[firstpage_image] =>[orig_patent_app_number] => 11182445
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/182445 | Formation of low resistance via contacts in interconnect structures | Jul 14, 2005 | Issued |
Array
(
[id] => 5793701
[patent_doc_number] => 20060014382
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-19
[patent_title] => 'Method for forming an interconnection line in a semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/181275
[patent_app_country] => US
[patent_app_date] => 2005-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2781
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0014/20060014382.pdf
[firstpage_image] =>[orig_patent_app_number] => 11181275
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/181275 | Method for forming an interconnection line in a semiconductor device | Jul 12, 2005 | Issued |
Array
(
[id] => 5075380
[patent_doc_number] => 20070015355
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-18
[patent_title] => 'Methods for forming interconnect structures'
[patent_app_type] => utility
[patent_app_number] => 11/179265
[patent_app_country] => US
[patent_app_date] => 2005-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2202
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0015/20070015355.pdf
[firstpage_image] =>[orig_patent_app_number] => 11179265
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/179265 | Methods for forming interconnect structures | Jul 11, 2005 | Issued |
Array
(
[id] => 4992242
[patent_doc_number] => 20070007586
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-11
[patent_title] => 'Method of forming a charge-trapping memory device'
[patent_app_type] => utility
[patent_app_number] => 11/177245
[patent_app_country] => US
[patent_app_date] => 2005-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3835
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0007/20070007586.pdf
[firstpage_image] =>[orig_patent_app_number] => 11177245
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/177245 | Method of forming a charge-trapping memory device | Jul 7, 2005 | Issued |
Array
(
[id] => 5738652
[patent_doc_number] => 20060009043
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-12
[patent_title] => 'Methods of forming a composite dielectric structure and methods of manufacturing a semiconductor device including a composite dielectric structure'
[patent_app_type] => utility
[patent_app_number] => 11/176715
[patent_app_country] => US
[patent_app_date] => 2005-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7612
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0009/20060009043.pdf
[firstpage_image] =>[orig_patent_app_number] => 11176715
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/176715 | Methods of forming a composite dielectric structure and methods of manufacturing a semiconductor device including a composite dielectric structure | Jul 6, 2005 | Issued |
Array
(
[id] => 817464
[patent_doc_number] => 07411272
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-08-12
[patent_title] => 'Semiconductor device and method of forming a semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/174605
[patent_app_country] => US
[patent_app_date] => 2005-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 42
[patent_figures_cnt] => 86
[patent_no_of_words] => 14650
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/411/07411272.pdf
[firstpage_image] =>[orig_patent_app_number] => 11174605
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/174605 | Semiconductor device and method of forming a semiconductor device | Jul 5, 2005 | Issued |
Array
(
[id] => 467222
[patent_doc_number] => 07235439
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-06-26
[patent_title] => 'Method of forming a MOS-controllable power semiconductor device for use in an integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 11/174606
[patent_app_country] => US
[patent_app_date] => 2005-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 42
[patent_figures_cnt] => 86
[patent_no_of_words] => 14497
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/235/07235439.pdf
[firstpage_image] =>[orig_patent_app_number] => 11174606
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/174606 | Method of forming a MOS-controllable power semiconductor device for use in an integrated circuit | Jul 5, 2005 | Issued |
Array
(
[id] => 390271
[patent_doc_number] => 07300867
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-11-27
[patent_title] => 'Dual damascene interconnect structures having different materials for line and via conductors'
[patent_app_type] => utility
[patent_app_number] => 11/174985
[patent_app_country] => US
[patent_app_date] => 2005-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 27
[patent_no_of_words] => 6241
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 237
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/300/07300867.pdf
[firstpage_image] =>[orig_patent_app_number] => 11174985
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/174985 | Dual damascene interconnect structures having different materials for line and via conductors | Jul 4, 2005 | Issued |
Array
(
[id] => 795597
[patent_doc_number] => 07429511
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-09-30
[patent_title] => 'Method of forming a tunneling insulating layer in nonvolatile memory device'
[patent_app_type] => utility
[patent_app_number] => 11/171706
[patent_app_country] => US
[patent_app_date] => 2005-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 17
[patent_no_of_words] => 4555
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/429/07429511.pdf
[firstpage_image] =>[orig_patent_app_number] => 11171706
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/171706 | Method of forming a tunneling insulating layer in nonvolatile memory device | Jun 29, 2005 | Issued |
Array
(
[id] => 797978
[patent_doc_number] => 07427565
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-09-23
[patent_title] => 'Multi-step etch for metal bump formation'
[patent_app_type] => utility
[patent_app_number] => 11/173245
[patent_app_country] => US
[patent_app_date] => 2005-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 17
[patent_no_of_words] => 3077
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/427/07427565.pdf
[firstpage_image] =>[orig_patent_app_number] => 11173245
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/173245 | Multi-step etch for metal bump formation | Jun 29, 2005 | Issued |
Array
(
[id] => 5139002
[patent_doc_number] => 20070001218
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-04
[patent_title] => 'Source side injection storage device with control gates adjacent to shared source/drain and method therefor'
[patent_app_type] => utility
[patent_app_number] => 11/170446
[patent_app_country] => US
[patent_app_date] => 2005-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3226
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0001/20070001218.pdf
[firstpage_image] =>[orig_patent_app_number] => 11170446
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/170446 | Source side injection storage device with control gates adjacent to shared source/drain and method therefor | Jun 28, 2005 | Issued |
Array
(
[id] => 563738
[patent_doc_number] => 07157772
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-01-02
[patent_title] => 'Semiconductor device and method of fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/167429
[patent_app_country] => US
[patent_app_date] => 2005-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 7917
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 338
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/157/07157772.pdf
[firstpage_image] =>[orig_patent_app_number] => 11167429
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/167429 | Semiconductor device and method of fabricating the same | Jun 27, 2005 | Issued |
Array
(
[id] => 267134
[patent_doc_number] => 07566659
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-07-28
[patent_title] => 'Method of forming fine pattern of semiconductor device using SiGe layer as sacrificial layer, and method of forming self-aligned contacts using the same'
[patent_app_type] => utility
[patent_app_number] => 11/157435
[patent_app_country] => US
[patent_app_date] => 2005-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 6709
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/566/07566659.pdf
[firstpage_image] =>[orig_patent_app_number] => 11157435
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/157435 | Method of forming fine pattern of semiconductor device using SiGe layer as sacrificial layer, and method of forming self-aligned contacts using the same | Jun 20, 2005 | Issued |
Array
(
[id] => 401175
[patent_doc_number] => 07291539
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-11-06
[patent_title] => 'Amorphization/templated recrystallization method for hybrid orientation substrates'
[patent_app_type] => utility
[patent_app_number] => 11/142646
[patent_app_country] => US
[patent_app_date] => 2005-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 44
[patent_no_of_words] => 6119
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/291/07291539.pdf
[firstpage_image] =>[orig_patent_app_number] => 11142646
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/142646 | Amorphization/templated recrystallization method for hybrid orientation substrates | May 31, 2005 | Issued |
Array
(
[id] => 5655981
[patent_doc_number] => 20060141717
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-29
[patent_title] => 'Method of forming isolation film in semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/139306
[patent_app_country] => US
[patent_app_date] => 2005-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2618
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0141/20060141717.pdf
[firstpage_image] =>[orig_patent_app_number] => 11139306
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/139306 | Method of forming isolation film in semiconductor device | May 26, 2005 | Abandoned |
Array
(
[id] => 7162274
[patent_doc_number] => 20050200024
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-15
[patent_title] => 'Method to generate porous organic dielectric'
[patent_app_type] => utility
[patent_app_number] => 11/125549
[patent_app_country] => US
[patent_app_date] => 2005-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1897
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0200/20050200024.pdf
[firstpage_image] =>[orig_patent_app_number] => 11125549
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/125549 | Method to generate porous organic dielectric | May 9, 2005 | Issued |
Array
(
[id] => 7108479
[patent_doc_number] => 20050205932
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-22
[patent_title] => 'Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates'
[patent_app_type] => utility
[patent_app_number] => 11/117424
[patent_app_country] => US
[patent_app_date] => 2005-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5152
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11117424
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/117424 | Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates | Apr 28, 2005 | Issued |
Array
(
[id] => 944103
[patent_doc_number] => 06967157
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-11-22
[patent_title] => 'Method of forming buried wiring in semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/109634
[patent_app_country] => US
[patent_app_date] => 2005-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 12
[patent_no_of_words] => 3478
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/967/06967157.pdf
[firstpage_image] =>[orig_patent_app_number] => 11109634
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/109634 | Method of forming buried wiring in semiconductor device | Apr 19, 2005 | Issued |
Array
(
[id] => 323011
[patent_doc_number] => 07518244
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-04-14
[patent_title] => 'Reducing line to line capacitance using oriented dielectric films'
[patent_app_type] => utility
[patent_app_number] => 11/103394
[patent_app_country] => US
[patent_app_date] => 2005-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 1178
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/518/07518244.pdf
[firstpage_image] =>[orig_patent_app_number] => 11103394
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/103394 | Reducing line to line capacitance using oriented dielectric films | Apr 10, 2005 | Issued |