
John D. Lee
Examiner (ID: 17114)
| Most Active Art Unit | 2501 |
| Art Unit(s) | 2874, 2606, 2507, 2501, 2504, 3621 |
| Total Applications | 2783 |
| Issued Applications | 2467 |
| Pending Applications | 118 |
| Abandoned Applications | 198 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7136936
[patent_doc_number] => 20050181600
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-18
[patent_title] => 'Method of forming a semiconductor device having a Ti/TiN/Ti<002>/a1<111> laminate'
[patent_app_type] => utility
[patent_app_number] => 11/101606
[patent_app_country] => US
[patent_app_date] => 2005-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2339
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0181/20050181600.pdf
[firstpage_image] =>[orig_patent_app_number] => 11101606
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/101606 | Method of forming a semiconductor device having a Ti/TiN/Ti<002>/a1<111> laminate | Apr 7, 2005 | Abandoned |
Array
(
[id] => 630788
[patent_doc_number] => 07132749
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-11-07
[patent_title] => 'Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment'
[patent_app_type] => utility
[patent_app_number] => 11/099255
[patent_app_country] => US
[patent_app_date] => 2005-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 13
[patent_no_of_words] => 4784
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/132/07132749.pdf
[firstpage_image] =>[orig_patent_app_number] => 11099255
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/099255 | Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment | Apr 4, 2005 | Issued |
Array
(
[id] => 7132903
[patent_doc_number] => 20050179076
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-18
[patent_title] => 'Method of forming DRAM capactiors with protected outside crown surface for more robust structures'
[patent_app_type] => utility
[patent_app_number] => 11/098112
[patent_app_country] => US
[patent_app_date] => 2005-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3906
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0179/20050179076.pdf
[firstpage_image] =>[orig_patent_app_number] => 11098112
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/098112 | DRAM capacitor structure with increased electrode support for preventing process damage and exposed electrode surface for increasing capacitor area | Apr 3, 2005 | Issued |
Array
(
[id] => 833435
[patent_doc_number] => 07396724
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-07-08
[patent_title] => 'Dual-hybrid liner formation without exposing silicide layer to photoresist stripping chemicals'
[patent_app_type] => utility
[patent_app_number] => 10/907415
[patent_app_country] => US
[patent_app_date] => 2005-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 2053
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/396/07396724.pdf
[firstpage_image] =>[orig_patent_app_number] => 10907415
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/907415 | Dual-hybrid liner formation without exposing silicide layer to photoresist stripping chemicals | Mar 30, 2005 | Issued |
Array
(
[id] => 151444
[patent_doc_number] => 07682954
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-03-23
[patent_title] => 'Method of impurity introduction, impurity introduction apparatus and semiconductor device produced with use of the method'
[patent_app_type] => utility
[patent_app_number] => 10/599205
[patent_app_country] => US
[patent_app_date] => 2005-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 5722
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/682/07682954.pdf
[firstpage_image] =>[orig_patent_app_number] => 10599205
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/599205 | Method of impurity introduction, impurity introduction apparatus and semiconductor device produced with use of the method | Mar 16, 2005 | Issued |
Array
(
[id] => 1076975
[patent_doc_number] => 07615488
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-11-10
[patent_title] => 'Method for forming pattern, thin film transistor, display device and method for manufacturing the same, and television device'
[patent_app_type] => utility
[patent_app_number] => 10/574616
[patent_app_country] => US
[patent_app_date] => 2005-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 71
[patent_no_of_words] => 31548
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 24
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/615/07615488.pdf
[firstpage_image] =>[orig_patent_app_number] => 10574616
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/574616 | Method for forming pattern, thin film transistor, display device and method for manufacturing the same, and television device | Mar 15, 2005 | Issued |
Array
(
[id] => 356233
[patent_doc_number] => 07488669
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-02-10
[patent_title] => 'Method to make markers for double gate SOI processing'
[patent_app_type] => utility
[patent_app_number] => 11/083356
[patent_app_country] => US
[patent_app_date] => 2005-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2251
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 228
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/488/07488669.pdf
[firstpage_image] =>[orig_patent_app_number] => 11083356
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/083356 | Method to make markers for double gate SOI processing | Mar 15, 2005 | Issued |
Array
(
[id] => 7039462
[patent_doc_number] => 20050158896
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-21
[patent_title] => 'Device transferring method'
[patent_app_type] => utility
[patent_app_number] => 11/079815
[patent_app_country] => US
[patent_app_date] => 2005-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 23808
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0158/20050158896.pdf
[firstpage_image] =>[orig_patent_app_number] => 11079815
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/079815 | Device transferring method | Mar 13, 2005 | Issued |
Array
(
[id] => 7036754
[patent_doc_number] => 20050156195
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-21
[patent_title] => 'Bipolar transistors with vertical structures'
[patent_app_type] => utility
[patent_app_number] => 11/079166
[patent_app_country] => US
[patent_app_date] => 2005-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 9221
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0156/20050156195.pdf
[firstpage_image] =>[orig_patent_app_number] => 11079166
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/079166 | Bipolar transistors with vertical structures | Mar 13, 2005 | Abandoned |
Array
(
[id] => 500272
[patent_doc_number] => 07205212
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-04-17
[patent_title] => 'Device transferring method'
[patent_app_type] => utility
[patent_app_number] => 11/079742
[patent_app_country] => US
[patent_app_date] => 2005-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 39
[patent_no_of_words] => 23844
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/205/07205212.pdf
[firstpage_image] =>[orig_patent_app_number] => 11079742
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/079742 | Device transferring method | Mar 13, 2005 | Issued |
Array
(
[id] => 7039461
[patent_doc_number] => 20050158895
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-21
[patent_title] => 'Device transferring method'
[patent_app_type] => utility
[patent_app_number] => 11/079780
[patent_app_country] => US
[patent_app_date] => 2005-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 23809
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0158/20050158895.pdf
[firstpage_image] =>[orig_patent_app_number] => 11079780
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/079780 | Device transferring method | Mar 13, 2005 | Issued |
Array
(
[id] => 7036839
[patent_doc_number] => 20050156273
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-21
[patent_title] => 'Memory devices'
[patent_app_type] => utility
[patent_app_number] => 11/079974
[patent_app_country] => US
[patent_app_date] => 2005-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2236
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0156/20050156273.pdf
[firstpage_image] =>[orig_patent_app_number] => 11079974
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/079974 | Memory devices | Mar 13, 2005 | Abandoned |
Array
(
[id] => 5780216
[patent_doc_number] => 20060202311
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-09-14
[patent_title] => 'LOW k DIELECTRIC CVD FILM FORMATION PROCESS WITH IN-SITU IMBEDDED NANOLAYERS TO IMPROVE MECHANICAL PROPERTIES'
[patent_app_type] => utility
[patent_app_number] => 10/906815
[patent_app_country] => US
[patent_app_date] => 2005-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 8087
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0202/20060202311.pdf
[firstpage_image] =>[orig_patent_app_number] => 10906815
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/906815 | Low k dielectric CVD film formation process with in-situ imbedded nanolayers to improve mechanical properties | Mar 7, 2005 | Issued |
Array
(
[id] => 7170599
[patent_doc_number] => 20050202655
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-15
[patent_title] => 'Method for manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/072265
[patent_app_country] => US
[patent_app_date] => 2005-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6327
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0202/20050202655.pdf
[firstpage_image] =>[orig_patent_app_number] => 11072265
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/072265 | Method for manufacturing semiconductor device | Mar 6, 2005 | Abandoned |
Array
(
[id] => 5705363
[patent_doc_number] => 20060194411
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-31
[patent_title] => 'Method to fabricate completely isolated silicon regions'
[patent_app_type] => utility
[patent_app_number] => 11/066206
[patent_app_country] => US
[patent_app_date] => 2005-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1974
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0194/20060194411.pdf
[firstpage_image] =>[orig_patent_app_number] => 11066206
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/066206 | Method to fabricate completely isolated silicon regions | Feb 24, 2005 | Issued |
Array
(
[id] => 318647
[patent_doc_number] => 07521357
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-04-21
[patent_title] => 'Methods of forming metal wiring in semiconductor devices using etch stop layers'
[patent_app_type] => utility
[patent_app_number] => 11/063936
[patent_app_country] => US
[patent_app_date] => 2005-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 23
[patent_no_of_words] => 5658
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/521/07521357.pdf
[firstpage_image] =>[orig_patent_app_number] => 11063936
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/063936 | Methods of forming metal wiring in semiconductor devices using etch stop layers | Feb 22, 2005 | Issued |
Array
(
[id] => 6944869
[patent_doc_number] => 20050196918
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-08
[patent_title] => 'DRAM memory and method for fabricating a DRAM memory cell'
[patent_app_type] => utility
[patent_app_number] => 11/055755
[patent_app_country] => US
[patent_app_date] => 2005-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 6615
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0196/20050196918.pdf
[firstpage_image] =>[orig_patent_app_number] => 11055755
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/055755 | DRAM memory and method for fabricating a DRAM memory cell | Feb 9, 2005 | Issued |
Array
(
[id] => 508785
[patent_doc_number] => 07199009
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-04-03
[patent_title] => 'Method for fabricating power mosfet'
[patent_app_type] => utility
[patent_app_number] => 10/906166
[patent_app_country] => US
[patent_app_date] => 2005-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 18
[patent_no_of_words] => 2761
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/199/07199009.pdf
[firstpage_image] =>[orig_patent_app_number] => 10906166
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/906166 | Method for fabricating power mosfet | Feb 4, 2005 | Issued |
| 11/046675 | Thin-film capacitor device | Jan 26, 2005 | Abandoned |
Array
(
[id] => 539171
[patent_doc_number] => 07173337
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-06
[patent_title] => 'Semiconductor device manufactured by the damascene process having improved stress migration resistance'
[patent_app_type] => utility
[patent_app_number] => 11/035745
[patent_app_country] => US
[patent_app_date] => 2005-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 39
[patent_no_of_words] => 11077
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 370
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/173/07173337.pdf
[firstpage_image] =>[orig_patent_app_number] => 11035745
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/035745 | Semiconductor device manufactured by the damascene process having improved stress migration resistance | Jan 17, 2005 | Issued |