
John D. Lee
Examiner (ID: 17114)
| Most Active Art Unit | 2501 |
| Art Unit(s) | 2874, 2606, 2507, 2501, 2504, 3621 |
| Total Applications | 2783 |
| Issued Applications | 2467 |
| Pending Applications | 118 |
| Abandoned Applications | 198 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7169091
[patent_doc_number] => 20050121726
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-09
[patent_title] => 'Semiconductor device and method for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/034948
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[pdf_file] => publications/A1/0121/20050121726.pdf
[firstpage_image] =>[orig_patent_app_number] => 11034948
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/034948 | Method for fabricating semiconductor device having high withstand voltage transistor | Jan 13, 2005 | Issued |
Array
(
[id] => 513122
[patent_doc_number] => 07196380
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[patent_kind] => B2
[patent_issue_date] => 2007-03-27
[patent_title] => 'High mobility plane FinFET with equal drive strength'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/905616 | High mobility plane FinFET with equal drive strength | Jan 12, 2005 | Issued |
Array
(
[id] => 5691688
[patent_doc_number] => 20060151833
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[patent_kind] => A1
[patent_issue_date] => 2006-07-13
[patent_title] => 'TRANSISTOR STRUCTURE HAVING STRESSED REGIONS OF OPPOSITE TYPES UNDERLYING CHANNEL AND SOURCE/DRAIN REGIONS'
[patent_app_type] => utility
[patent_app_number] => 10/905586
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[patent_app_date] => 2005-01-12
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/905586 | Transistor structure having stressed regions of opposite types underlying channel and source/drain regions | Jan 11, 2005 | Issued |
Array
(
[id] => 195867
[patent_doc_number] => 07635645
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[patent_kind] => B2
[patent_issue_date] => 2009-12-22
[patent_title] => 'Method for forming interconnection line in semiconductor device and interconnection line structure'
[patent_app_type] => utility
[patent_app_number] => 11/028515
[patent_app_country] => US
[patent_app_date] => 2005-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/028515 | Method for forming interconnection line in semiconductor device and interconnection line structure | Jan 3, 2005 | Issued |
Array
(
[id] => 512651
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[patent_issue_date] => 2007-04-03
[patent_title] => 'Integrated low-k hard mask'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/028884 | Integrated low-k hard mask | Jan 2, 2005 | Issued |
Array
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[patent_title] => 'Dielectric layer for semiconductor device and method of manufacturing the same'
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Array
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[patent_title] => 'Semiconductor constructions'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/018848 | Semiconductor constructions | Dec 19, 2004 | Issued |
Array
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[patent_title] => 'Methodology for recovery of hot carrier induced degradation in bipolar devices'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/904985 | Methodology for recovery of hot carrier induced degradation in bipolar devices | Dec 7, 2004 | Issued |
Array
(
[id] => 602773
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[patent_title] => 'LED with self aligned bond pad'
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[patent_app_number] => 10/996666
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[firstpage_image] =>[orig_patent_app_number] => 10996666
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/996666 | LED with self aligned bond pad | Nov 23, 2004 | Issued |
Array
(
[id] => 677050
[patent_doc_number] => 07087948
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[patent_issue_date] => 2006-08-08
[patent_title] => 'Forming electronic structures having dual dielectric thicknesses and the structure so formed'
[patent_app_type] => utility
[patent_app_number] => 10/995444
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/995444 | Forming electronic structures having dual dielectric thicknesses and the structure so formed | Nov 22, 2004 | Issued |
Array
(
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[patent_doc_number] => 20050116292
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[patent_title] => 'Thin film transistor using a metal induced crystallization process and method for fabricating the same and active matrix flat panel display using the thin film transistor'
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[patent_app_number] => 10/992856
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/992856 | Thin film transistor using a metal induced crystallization process and method for fabricating the same and active matrix flat panel display using the thin film transistor | Nov 21, 2004 | Issued |
Array
(
[id] => 7010910
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[patent_title] => 'Connection components with anistropic conductive material interconnector'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/994695 | Connection components with anistropic conductive material interconnector | Nov 21, 2004 | Abandoned |
Array
(
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Array
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Array
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Array
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[patent_title] => 'High voltage N-LDMOS transistors having shallow trench isolation region'
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Array
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Array
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Array
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