Search

John D. Lee

Examiner (ID: 17114)

Most Active Art Unit
2501
Art Unit(s)
2874, 2606, 2507, 2501, 2504, 3621
Total Applications
2783
Issued Applications
2467
Pending Applications
118
Abandoned Applications
198

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7169091 [patent_doc_number] => 20050121726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/034948 [patent_app_country] => US [patent_app_date] => 2005-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8745 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20050121726.pdf [firstpage_image] =>[orig_patent_app_number] => 11034948 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/034948
Method for fabricating semiconductor device having high withstand voltage transistor Jan 13, 2005 Issued
Array ( [id] => 513122 [patent_doc_number] => 07196380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-27 [patent_title] => 'High mobility plane FinFET with equal drive strength' [patent_app_type] => utility [patent_app_number] => 10/905616 [patent_app_country] => US [patent_app_date] => 2005-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 2731 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/196/07196380.pdf [firstpage_image] =>[orig_patent_app_number] => 10905616 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/905616
High mobility plane FinFET with equal drive strength Jan 12, 2005 Issued
Array ( [id] => 5691688 [patent_doc_number] => 20060151833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'TRANSISTOR STRUCTURE HAVING STRESSED REGIONS OF OPPOSITE TYPES UNDERLYING CHANNEL AND SOURCE/DRAIN REGIONS' [patent_app_type] => utility [patent_app_number] => 10/905586 [patent_app_country] => US [patent_app_date] => 2005-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3648 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20060151833.pdf [firstpage_image] =>[orig_patent_app_number] => 10905586 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/905586
Transistor structure having stressed regions of opposite types underlying channel and source/drain regions Jan 11, 2005 Issued
Array ( [id] => 195867 [patent_doc_number] => 07635645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-22 [patent_title] => 'Method for forming interconnection line in semiconductor device and interconnection line structure' [patent_app_type] => utility [patent_app_number] => 11/028515 [patent_app_country] => US [patent_app_date] => 2005-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4106 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/635/07635645.pdf [firstpage_image] =>[orig_patent_app_number] => 11028515 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/028515
Method for forming interconnection line in semiconductor device and interconnection line structure Jan 3, 2005 Issued
Array ( [id] => 512651 [patent_doc_number] => 07199473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-03 [patent_title] => 'Integrated low-k hard mask' [patent_app_type] => utility [patent_app_number] => 11/028884 [patent_app_country] => US [patent_app_date] => 2005-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 4343 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/199/07199473.pdf [firstpage_image] =>[orig_patent_app_number] => 11028884 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/028884
Integrated low-k hard mask Jan 2, 2005 Issued
Array ( [id] => 6981116 [patent_doc_number] => 20050151184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-14 [patent_title] => 'Dielectric layer for semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/027256 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4672 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20050151184.pdf [firstpage_image] =>[orig_patent_app_number] => 11027256 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/027256
Dielectric layer for semiconductor device and method of manufacturing the same Dec 29, 2004 Issued
Array ( [id] => 6996818 [patent_doc_number] => 20050136596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Semiconductor constructions' [patent_app_type] => utility [patent_app_number] => 11/018848 [patent_app_country] => US [patent_app_date] => 2004-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3184 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20050136596.pdf [firstpage_image] =>[orig_patent_app_number] => 11018848 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/018848
Semiconductor constructions Dec 19, 2004 Issued
Array ( [id] => 5838254 [patent_doc_number] => 20060118912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Methodology for recovery of hot carrier induced degradation in bipolar devices' [patent_app_type] => utility [patent_app_number] => 10/904985 [patent_app_country] => US [patent_app_date] => 2004-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3512 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20060118912.pdf [firstpage_image] =>[orig_patent_app_number] => 10904985 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/904985
Methodology for recovery of hot carrier induced degradation in bipolar devices Dec 7, 2004 Issued
Array ( [id] => 602773 [patent_doc_number] => 07432536 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-07 [patent_title] => 'LED with self aligned bond pad' [patent_app_type] => utility [patent_app_number] => 10/996666 [patent_app_country] => US [patent_app_date] => 2004-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2146 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/432/07432536.pdf [firstpage_image] =>[orig_patent_app_number] => 10996666 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/996666
LED with self aligned bond pad Nov 23, 2004 Issued
Array ( [id] => 677050 [patent_doc_number] => 07087948 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-08 [patent_title] => 'Forming electronic structures having dual dielectric thicknesses and the structure so formed' [patent_app_type] => utility [patent_app_number] => 10/995444 [patent_app_country] => US [patent_app_date] => 2004-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 37 [patent_no_of_words] => 5179 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/087/07087948.pdf [firstpage_image] =>[orig_patent_app_number] => 10995444 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/995444
Forming electronic structures having dual dielectric thicknesses and the structure so formed Nov 22, 2004 Issued
Array ( [id] => 7140111 [patent_doc_number] => 20050116292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-02 [patent_title] => 'Thin film transistor using a metal induced crystallization process and method for fabricating the same and active matrix flat panel display using the thin film transistor' [patent_app_type] => utility [patent_app_number] => 10/992856 [patent_app_country] => US [patent_app_date] => 2004-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3332 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20050116292.pdf [firstpage_image] =>[orig_patent_app_number] => 10992856 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/992856
Thin film transistor using a metal induced crystallization process and method for fabricating the same and active matrix flat panel display using the thin film transistor Nov 21, 2004 Issued
Array ( [id] => 7010910 [patent_doc_number] => 20050064626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-24 [patent_title] => 'Connection components with anistropic conductive material interconnector' [patent_app_type] => utility [patent_app_number] => 10/994695 [patent_app_country] => US [patent_app_date] => 2004-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8502 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20050064626.pdf [firstpage_image] =>[orig_patent_app_number] => 10994695 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/994695
Connection components with anistropic conductive material interconnector Nov 21, 2004 Abandoned
Array ( [id] => 6915474 [patent_doc_number] => 20050093035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Semiconductor device and manufacturing method of semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/991485 [patent_app_country] => US [patent_app_date] => 2004-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9679 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20050093035.pdf [firstpage_image] =>[orig_patent_app_number] => 10991485 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/991485
Semiconductor device and manufacturing method of semiconductor device Nov 18, 2004 Issued
Array ( [id] => 6936558 [patent_doc_number] => 20050110119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'Integrated circuit chip' [patent_app_type] => utility [patent_app_number] => 10/991476 [patent_app_country] => US [patent_app_date] => 2004-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6068 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20050110119.pdf [firstpage_image] =>[orig_patent_app_number] => 10991476 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/991476
Integrated circuit chip having a seal ring, a ground ring and a guard ring Nov 18, 2004 Issued
Array ( [id] => 7144273 [patent_doc_number] => 20050118804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-02 [patent_title] => 'Formation of boride barrier layers using chemisorption techniques' [patent_app_type] => utility [patent_app_number] => 10/993925 [patent_app_country] => US [patent_app_date] => 2004-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4592 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20050118804.pdf [firstpage_image] =>[orig_patent_app_number] => 10993925 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/993925
Formation of boride barrier layers using chemisorption techniques Nov 18, 2004 Issued
Array ( [id] => 6991012 [patent_doc_number] => 20050090049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-28 [patent_title] => 'High voltage N-LDMOS transistors having shallow trench isolation region' [patent_app_type] => utility [patent_app_number] => 10/991936 [patent_app_country] => US [patent_app_date] => 2004-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3255 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20050090049.pdf [firstpage_image] =>[orig_patent_app_number] => 10991936 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/991936
Method of forming high voltage N-LDMOS transistors having shallow trench isolation region with drain extensions Nov 17, 2004 Issued
Array ( [id] => 504859 [patent_doc_number] => 07202156 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-10 [patent_title] => 'Process for manufacturing a wiring substrate' [patent_app_type] => utility [patent_app_number] => 10/989515 [patent_app_country] => US [patent_app_date] => 2004-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3923 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/202/07202156.pdf [firstpage_image] =>[orig_patent_app_number] => 10989515 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/989515
Process for manufacturing a wiring substrate Nov 16, 2004 Issued
Array ( [id] => 5898251 [patent_doc_number] => 20060043484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Self-aligned silicide (salicide) process for low resistivity contacts to thin film silicon-on-insulator and bulk mosfets and for shallow junctions' [patent_app_type] => utility [patent_app_number] => 10/989639 [patent_app_country] => US [patent_app_date] => 2004-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7000 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20060043484.pdf [firstpage_image] =>[orig_patent_app_number] => 10989639 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/989639
Self-aligned silicide (salicide) process for low resistivity contacts to thin film silicon-on-insulator and bulk mosfets and for shallow junctions Nov 16, 2004 Abandoned
Array ( [id] => 860220 [patent_doc_number] => 07371610 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-05-13 [patent_title] => 'Process for fabricating an integrated circuit package with reduced mold warping' [patent_app_type] => utility [patent_app_number] => 10/990008 [patent_app_country] => US [patent_app_date] => 2004-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 32 [patent_no_of_words] => 3836 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/371/07371610.pdf [firstpage_image] =>[orig_patent_app_number] => 10990008 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/990008
Process for fabricating an integrated circuit package with reduced mold warping Nov 15, 2004 Issued
Array ( [id] => 496730 [patent_doc_number] => 07208356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-24 [patent_title] => 'Method of manufacturing multiple-gate MOS transistor having an improved channel structure' [patent_app_type] => utility [patent_app_number] => 10/989006 [patent_app_country] => US [patent_app_date] => 2004-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 32 [patent_no_of_words] => 4692 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/208/07208356.pdf [firstpage_image] =>[orig_patent_app_number] => 10989006 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/989006
Method of manufacturing multiple-gate MOS transistor having an improved channel structure Nov 15, 2004 Issued
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