John D. Lee

Array ( [id] => 6988768 [patent_doc_number] => 20050087862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-28 [patent_title] => 'Electronic component package and method of manufacturing same' [patent_app_type] => utility [patent_app_number] => 10/989675 [patent_app_country] => US [patent_app_date] => 2004-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5966 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20050087862.pdf [firstpage_image] =>[orig_patent_app_number] => 10989675 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5776891 [patent_doc_number] => 20060105531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-18 [patent_title] => 'Method of forming notched gate structure' [patent_app_type] => utility [patent_app_number] => 10/986765 [patent_app_country] => US [patent_app_date] => 2004-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1547 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20060105531.pdf [firstpage_image] =>[orig_patent_app_number] => 10986765 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5776921 [patent_doc_number] => 20060105561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-18 [patent_title] => 'Method of manufacturing a self-aligned contact structure' [patent_app_type] => utility [patent_app_number] => 10/986906 [patent_app_country] => US [patent_app_date] => 2004-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1633 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20060105561.pdf [firstpage_image] =>[orig_patent_app_number] => 10986906 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7094784 [patent_doc_number] => 20050127427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Method and structure to improve the gate coupling ratio (GCR) for manufacturing a flash memory device' [patent_app_type] => utility [patent_app_number] => 10/986840 [patent_app_country] => US [patent_app_date] => 2004-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2607 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20050127427.pdf [firstpage_image] =>[orig_patent_app_number] => 10986840 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7074909 [patent_doc_number] => 20050148177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Method and an apparatus for manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/986406 [patent_app_country] => US [patent_app_date] => 2004-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3697 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20050148177.pdf [firstpage_image] =>[orig_patent_app_number] => 10986406 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6931285 [patent_doc_number] => 20050282320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-22 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/986225 [patent_app_country] => US [patent_app_date] => 2004-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1717 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20050282320.pdf [firstpage_image] =>[orig_patent_app_number] => 10986225 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 515201 [patent_doc_number] => 07192881 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-20 [patent_title] => 'Method of forming sidewall spacer elements for a circuit element by increasing an etch selectivity' [patent_app_type] => utility [patent_app_number] => 10/987466 [patent_app_country] => US [patent_app_date] => 2004-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5482 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/192/07192881.pdf [firstpage_image] =>[orig_patent_app_number] => 10987466 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 359606 [patent_doc_number] => 07485485 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-03 [patent_title] => 'Method and apparatus for making a MEMS scanner' [patent_app_type] => utility [patent_app_number] => 10/986635 [patent_app_country] => US [patent_app_date] => 2004-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 10070 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/485/07485485.pdf [firstpage_image] =>[orig_patent_app_number] => 10986635 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6939241 [patent_doc_number] => 20050112804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'Silicide-silicon oxide-semiconductor antifuse device and method of making' [patent_app_type] => utility [patent_app_number] => 10/986196 [patent_app_country] => US [patent_app_date] => 2004-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7064 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20050112804.pdf [firstpage_image] =>[orig_patent_app_number] => 10986196 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 373311 [patent_doc_number] => 07473614 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-06 [patent_title] => 'Method for manufacturing a silicon-on-insulator (SOI) wafer with an etch stop layer' [patent_app_type] => utility [patent_app_number] => 10/987775 [patent_app_country] => US [patent_app_date] => 2004-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 4889 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/473/07473614.pdf [firstpage_image] =>[orig_patent_app_number] => 10987775 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5865623 [patent_doc_number] => 20060099753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'METHOD OF FORMING DEVICES HAVING THREE DIFFERENT OPERATION VOLTAGES' [patent_app_type] => utility [patent_app_number] => 10/904455 [patent_app_country] => US [patent_app_date] => 2004-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 1981 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20060099753.pdf [firstpage_image] =>[orig_patent_app_number] => 10904455 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 440184 [patent_doc_number] => 07259424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-21 [patent_title] => 'Semiconductor device having a trench with a step-free insulation film' [patent_app_type] => utility [patent_app_number] => 10/984925 [patent_app_country] => US [patent_app_date] => 2004-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 5742 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/259/07259424.pdf [firstpage_image] =>[orig_patent_app_number] => 10984925 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7104126 [patent_doc_number] => 20050106852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Air gap interconnect structure and method' [patent_app_type] => utility [patent_app_number] => 10/986414 [patent_app_country] => US [patent_app_date] => 2004-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4541 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20050106852.pdf [firstpage_image] =>[orig_patent_app_number] => 10986414 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5863267 [patent_doc_number] => 20060097397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Method for forming a dual layer, low resistance metallization during the formation of a semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/985635 [patent_app_country] => US [patent_app_date] => 2004-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3339 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20060097397.pdf [firstpage_image] =>[orig_patent_app_number] => 10985635 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7140177 [patent_doc_number] => 20050116327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-02 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/983706 [patent_app_country] => US [patent_app_date] => 2004-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7321 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20050116327.pdf [firstpage_image] =>[orig_patent_app_number] => 10983706 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5805116 [patent_doc_number] => 20060091468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Top and sidewall bridged interconnect structure and method' [patent_app_type] => utility [patent_app_number] => 10/982455 [patent_app_country] => US [patent_app_date] => 2004-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4156 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20060091468.pdf [firstpage_image] =>[orig_patent_app_number] => 10982455 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5807816 [patent_doc_number] => 20060094171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Isolation trench thermal annealing method for non-bulk silicon semiconductor substrate' [patent_app_type] => utility [patent_app_number] => 10/982456 [patent_app_country] => US [patent_app_date] => 2004-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2570 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20060094171.pdf [firstpage_image] =>[orig_patent_app_number] => 10982456 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7169242 [patent_doc_number] => 20050121786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Semiconductor device and its manufacturing method' [patent_app_type] => utility [patent_app_number] => 10/979326 [patent_app_country] => US [patent_app_date] => 2004-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6169 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20050121786.pdf [firstpage_image] =>[orig_patent_app_number] => 10979326 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 833470 [patent_doc_number] => 07396759 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-07-08 [patent_title] => 'Protection of Cu damascene interconnects by formation of a self-aligned buffer layer' [patent_app_type] => utility [patent_app_number] => 10/980076 [patent_app_country] => US [patent_app_date] => 2004-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 6445 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/396/07396759.pdf [firstpage_image] =>[orig_patent_app_number] => 10980076 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6996407 [patent_doc_number] => 20050136185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Post rinse to improve selective deposition of electroless cobalt on copper for ULSI application' [patent_app_type] => utility [patent_app_number] => 10/979078 [patent_app_country] => US [patent_app_date] => 2004-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6636 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20050136185.pdf [firstpage_image] =>[orig_patent_app_number] => 10979078 [rel_patent_id] =>[rel_patent_doc_number] =>)