Search

John D. Lee

Examiner (ID: 17114)

Most Active Art Unit
2501
Art Unit(s)
2874, 2606, 2507, 2501, 2504, 3621
Total Applications
2783
Issued Applications
2467
Pending Applications
118
Abandoned Applications
198

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6915463 [patent_doc_number] => 20050093024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 10/975919 [patent_app_country] => US [patent_app_date] => 2004-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4941 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20050093024.pdf [firstpage_image] =>[orig_patent_app_number] => 10975919 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/975919
Semiconductor device and method for manufacturing the same Oct 25, 2004 Abandoned
Array ( [id] => 5741316 [patent_doc_number] => 20060087039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-27 [patent_title] => 'UBM STRUCTURE FOR IMPROVING RELIABILITY AND PERFORMANCE' [patent_app_type] => utility [patent_app_number] => 10/904096 [patent_app_country] => US [patent_app_date] => 2004-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3207 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20060087039.pdf [firstpage_image] =>[orig_patent_app_number] => 10904096 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/904096
UBM STRUCTURE FOR IMPROVING RELIABILITY AND PERFORMANCE Oct 21, 2004 Abandoned
Array ( [id] => 7161983 [patent_doc_number] => 20050085046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Method of forming poly insulator poly capacitors by using a self-aligned salicide process' [patent_app_type] => utility [patent_app_number] => 10/967198 [patent_app_country] => US [patent_app_date] => 2004-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1495 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20050085046.pdf [firstpage_image] =>[orig_patent_app_number] => 10967198 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/967198
Method of forming poly insulator poly capacitors by using a self-aligned salicide process Oct 18, 2004 Issued
Array ( [id] => 446130 [patent_doc_number] => 07253099 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-07 [patent_title] => 'Method of manufacturing semiconductor device that includes forming self-aligned contact pad' [patent_app_type] => utility [patent_app_number] => 10/957305 [patent_app_country] => US [patent_app_date] => 2004-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5572 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/253/07253099.pdf [firstpage_image] =>[orig_patent_app_number] => 10957305 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/957305
Method of manufacturing semiconductor device that includes forming self-aligned contact pad Sep 29, 2004 Issued
Array ( [id] => 411553 [patent_doc_number] => 07282418 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-10-16 [patent_title] => 'Method for fabricating a self-aligned bipolar transistor without spacers' [patent_app_type] => utility [patent_app_number] => 10/952256 [patent_app_country] => US [patent_app_date] => 2004-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 5235 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/282/07282418.pdf [firstpage_image] =>[orig_patent_app_number] => 10952256 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/952256
Method for fabricating a self-aligned bipolar transistor without spacers Sep 27, 2004 Issued
Array ( [id] => 798185 [patent_doc_number] => 07427773 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-23 [patent_title] => 'Layer transfer of low defect SiGe using an etch-back process' [patent_app_type] => utility [patent_app_number] => 10/948421 [patent_app_country] => US [patent_app_date] => 2004-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 21 [patent_no_of_words] => 3991 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/427/07427773.pdf [firstpage_image] =>[orig_patent_app_number] => 10948421 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/948421
Layer transfer of low defect SiGe using an etch-back process Sep 22, 2004 Issued
Array ( [id] => 813717 [patent_doc_number] => 07413989 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-19 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/944866 [patent_app_country] => US [patent_app_date] => 2004-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 5036 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/413/07413989.pdf [firstpage_image] =>[orig_patent_app_number] => 10944866 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/944866
Method of manufacturing semiconductor device Sep 20, 2004 Issued
Array ( [id] => 5708180 [patent_doc_number] => 20060049524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-09 [patent_title] => 'Post passivation interconnection process and structures' [patent_app_type] => utility [patent_app_number] => 10/937543 [patent_app_country] => US [patent_app_date] => 2004-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7652 [patent_no_of_claims] => 83 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20060049524.pdf [firstpage_image] =>[orig_patent_app_number] => 10937543 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/937543
Post passivation interconnection process and structures Sep 8, 2004 Issued
Array ( [id] => 7212777 [patent_doc_number] => 20050054178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Electric device, its manufacturing method, and electronic equipment' [patent_app_type] => utility [patent_app_number] => 10/936826 [patent_app_country] => US [patent_app_date] => 2004-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6233 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20050054178.pdf [firstpage_image] =>[orig_patent_app_number] => 10936826 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/936826
Electric device, its manufacturing method, and electronic equipment Sep 8, 2004 Abandoned
Array ( [id] => 847103 [patent_doc_number] => 07384803 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-10 [patent_title] => 'Method of manufacturing nitride semiconductor device including SiC substrate and apparatus for manufacturing nitride semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/932028 [patent_app_country] => US [patent_app_date] => 2004-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 11276 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/384/07384803.pdf [firstpage_image] =>[orig_patent_app_number] => 10932028 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/932028
Method of manufacturing nitride semiconductor device including SiC substrate and apparatus for manufacturing nitride semiconductor device Sep 1, 2004 Issued
Array ( [id] => 7191605 [patent_doc_number] => 20050040533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-24 [patent_title] => 'Semiconductor devices including porous insulators' [patent_app_type] => utility [patent_app_number] => 10/932835 [patent_app_country] => US [patent_app_date] => 2004-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7884 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20050040533.pdf [firstpage_image] =>[orig_patent_app_number] => 10932835 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/932835
Semiconductor devices including porous insulators Aug 31, 2004 Issued
Array ( [id] => 876205 [patent_doc_number] => 07358180 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-15 [patent_title] => 'Method of forming wiring structure and semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/927006 [patent_app_country] => US [patent_app_date] => 2004-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 27 [patent_no_of_words] => 6778 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/358/07358180.pdf [firstpage_image] =>[orig_patent_app_number] => 10927006 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/927006
Method of forming wiring structure and semiconductor device Aug 26, 2004 Issued
Array ( [id] => 935423 [patent_doc_number] => 06974772 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-13 [patent_title] => 'Integrated low-k hard mask' [patent_app_type] => utility [patent_app_number] => 10/922619 [patent_app_country] => US [patent_app_date] => 2004-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 4320 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/974/06974772.pdf [firstpage_image] =>[orig_patent_app_number] => 10922619 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/922619
Integrated low-k hard mask Aug 18, 2004 Issued
Array ( [id] => 7620076 [patent_doc_number] => 06943107 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-13 [patent_title] => 'Methods of forming a refractory metal silicide' [patent_app_type] => utility [patent_app_number] => 10/915935 [patent_app_country] => US [patent_app_date] => 2004-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 3905 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/943/06943107.pdf [firstpage_image] =>[orig_patent_app_number] => 10915935 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/915935
Methods of forming a refractory metal silicide Aug 9, 2004 Issued
Array ( [id] => 5878107 [patent_doc_number] => 20060027901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-09 [patent_title] => 'Stacked chip package with exposed lead-frame bottom surface' [patent_app_type] => utility [patent_app_number] => 10/913319 [patent_app_country] => US [patent_app_date] => 2004-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2835 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20060027901.pdf [firstpage_image] =>[orig_patent_app_number] => 10913319 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/913319
Stacked chip package with exposed lead-frame bottom surface Aug 8, 2004 Abandoned
Array ( [id] => 487426 [patent_doc_number] => 07217970 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-15 [patent_title] => 'Devices containing platinum-iridium films and methods of preparing such films and devices' [patent_app_type] => utility [patent_app_number] => 10/912906 [patent_app_country] => US [patent_app_date] => 2004-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10287 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/217/07217970.pdf [firstpage_image] =>[orig_patent_app_number] => 10912906 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/912906
Devices containing platinum-iridium films and methods of preparing such films and devices Aug 5, 2004 Issued
Array ( [id] => 5817973 [patent_doc_number] => 20060022286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'Ferromagnetic liner for conductive lines of magnetic memory cells' [patent_app_type] => utility [patent_app_number] => 10/903356 [patent_app_country] => US [patent_app_date] => 2004-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7862 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20060022286.pdf [firstpage_image] =>[orig_patent_app_number] => 10903356 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/903356
Ferromagnetic liner for conductive lines of magnetic memory cells Jul 29, 2004 Abandoned
Array ( [id] => 500158 [patent_doc_number] => 07205189 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-17 [patent_title] => 'Method of manufacturing a dual bit flash memory' [patent_app_type] => utility [patent_app_number] => 10/710672 [patent_app_country] => US [patent_app_date] => 2004-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 3262 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/205/07205189.pdf [firstpage_image] =>[orig_patent_app_number] => 10710672 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/710672
Method of manufacturing a dual bit flash memory Jul 27, 2004 Issued
Array ( [id] => 7154724 [patent_doc_number] => 20050026376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'Methods for forming shallow trench isolation' [patent_app_type] => utility [patent_app_number] => 10/900685 [patent_app_country] => US [patent_app_date] => 2004-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1907 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20050026376.pdf [firstpage_image] =>[orig_patent_app_number] => 10900685 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/900685
Methods for forming shallow trench isolation Jul 27, 2004 Issued
Array ( [id] => 6915544 [patent_doc_number] => 20050093105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Semiconductor-on-insulator chip with<100>-oriented transistors' [patent_app_type] => utility [patent_app_number] => 10/901763 [patent_app_country] => US [patent_app_date] => 2004-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2782 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20050093105.pdf [firstpage_image] =>[orig_patent_app_number] => 10901763 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/901763
Semiconductor-on-insulator chip with<100>-oriented transistors Jul 27, 2004 Issued
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